Searched refs:RCC_CCIPR1_SPI1SEL_Pos (Results 1 – 18 of 18) sorted by relevance
447 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16…448 …K ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_…449 … ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_…546 … ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_C…
571 #define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos <…572 #define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos <…573 … (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */574 #define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos <…575 … (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */576 #define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos <…577 … (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */823 #define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 1…824 … (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
10295 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro10296 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000…10298 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000…10299 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000…
10603 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro10604 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000…10606 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000…10607 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000…
10621 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro10622 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000…10624 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000…10625 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000…
15658 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro15659 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…15661 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…15662 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
15109 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro15110 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…15112 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…15113 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
16618 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro16619 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…16621 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…16622 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
17225 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro17226 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…17228 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…17229 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
17703 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro17704 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…17706 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…17707 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
18310 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro18311 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…18313 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…18314 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
19293 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro19294 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…19296 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…19297 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
21471 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro21472 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…21474 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…21475 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
19900 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro19901 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…19903 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…19904 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
22431 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro22432 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…22434 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…22435 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
22078 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro22079 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…22081 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…22082 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
23038 #define RCC_CCIPR1_SPI1SEL_Pos (20U) macro23039 #define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0030000…23041 #define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0010000…23042 #define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x0020000…
