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Searched refs:RCC_CCIPR1_I2C1SEL_0 (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc_ex.h634 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0
636 #define RCC_I2C1CLKSOURCE_MSIK (RCC_CCIPR1_I2C1SEL_1 | RCC_CCIPR1_I2C1SEL_0)
Dstm32u5xx_ll_rcc.h520 … (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc_ex.h224 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0
Dstm32wbaxx_ll_rcc.h434 … ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIP…
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc_ex.h358 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 /*!< System clock */
Dstm32l5xx_ll_rcc.h418 …SET_CCIPR1 << 24U) | ((uint32_t)RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIP…
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h10288 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400… macro
Dstm32wba54xx.h10596 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400… macro
Dstm32wba5mxx.h10614 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400… macro
Dstm32wba55xx.h10614 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400… macro
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h12095 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00001000 */ macro
Dstm32l562xx.h12825 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00001000 */ macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h15636 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u535xx.h15087 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u575xx.h16596 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u585xx.h17203 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u595xx.h17681 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5a5xx.h18288 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5f7xx.h19271 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u599xx.h21449 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5g7xx.h19878 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5f9xx.h22409 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5a9xx.h22056 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro
Dstm32u5g9xx.h23016 #define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x0000040… macro