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Searched refs:RCC_APBENR1_CRSEN (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h853 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
855 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
914 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN)
1074 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
1097 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
Dstm32c0xx_ll_bus.h101 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h954 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
956 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1102 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN)
1312 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
1374 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
Dstm32u0xx_ll_bus.h119 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1056 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1058 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1382 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
1540 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
1604 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
Dstm32g0xx_ll_bus.h134 #define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c071xx.h4718 #define RCC_APBENR1_CRSEN RCC_APBENR1_CRSEN_Msk macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u083xx.h6218 #define RCC_APBENR1_CRSEN RCC_APBENR1_CRSEN_Msk macro
Dstm32u073xx.h5954 #define RCC_APBENR1_CRSEN RCC_APBENR1_CRSEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g0c1xx.h6838 #define RCC_APBENR1_CRSEN RCC_APBENR1_CRSEN_Msk macro
Dstm32g0b1xx.h6590 #define RCC_APBENR1_CRSEN RCC_APBENR1_CRSEN_Msk macro