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Searched refs:RCC_APB1ENR_PWREN (Results 1 – 25 of 143) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc.h447 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
449 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
454 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
504 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
507 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f7xx_ll_bus.h184 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h440 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
442 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
453 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
479 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
480 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f1xx_ll_bus.h122 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h753 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
755 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
763 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
779 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
784 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f0xx_ll_bus.h141 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
524 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
542 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
550 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f4xx_ll_bus.h256 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
835 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
938 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
947 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Dstm32f3xx_ll_bus.h169 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dsystem_stm32l1xx.c278 RCC->APB1ENR |= RCC_APB1ENR_PWREN; in SystemInit_ExtMemCtl()
281 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); in SystemInit_ExtMemCtl()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h766 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
769 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
838 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != 0U)
840 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) == 0U)
Dstm32l0xx_ll_bus.h130 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h805 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
807 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
838 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
1153 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U)
1168 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U)
Dstm32l1xx_ll_bus.h135 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h803 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
805 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
835 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
869 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
893 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
Dstm32f2xx_ll_bus.h151 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h1179 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface… macro
Dstm32f101xb.h1212 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface… macro
Dstm32f100xb.h1302 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3125 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enabl… macro
Dstm32f030x8.h3169 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enabl… macro
Dstm32f070x6.h3196 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enabl… macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3811 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enabl… macro
Dstm32l010x8.h3510 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enabl… macro

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