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Searched refs:RCC_APB1ENR_I2C2EN (Results 1 – 25 of 126) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h2027 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2029 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2042 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2092 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2094 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2104 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2194 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2196 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
2223 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2517 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
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Dstm32f3xx_ll_bus.h158 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_bus.h140 RCC_APB1ENR_I2C2EN)
149 RCC_APB1ENR_I2C2EN)
178 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h707 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
717 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
727 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)
736 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)
786 #define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
801 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
816 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) != 0U)
830 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN) == 0U)
Dstm32l0xx_ll_bus.h122 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
523 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
541 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
549 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Dstm32f4xx_ll_bus.h237 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h1082 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1084 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1089 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1588 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1590 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Dstm32f0xx_ll_bus.h130 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h791 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
793 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
836 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1151 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U)
1166 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U)
Dstm32l1xx_ll_bus.h133 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h820 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
822 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
829 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1086 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1087 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Dstm32f1xx_ll_bus.h120 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h775 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
777 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
833 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
867 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
891 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
Dstm32f2xx_ll_bus.h147 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_hal_rcc_ex.c689 if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN) in HAL_RCCEx_GetPeriphCLKFreq()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1078 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1080 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
1186 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
1603 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1630 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Dstm32f7xx_ll_bus.h169 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x8.h3166 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enab… macro
Dstm32f030xc.h3468 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enab… macro
Dstm32f070xb.h3324 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enab… macro
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101xb.h1225 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock ena… macro
Dstm32f100xb.h1315 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock ena… macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l051xx.h3778 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enab… macro
Dstm32l081xx.h3999 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enab… macro

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