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Searched refs:RCC_AHBENR_DMA2EN (Results 1 – 25 of 50) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc_ex.h201 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
203 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
207 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
642 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)
643 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)
Dstm32l1xx_ll_bus.h92 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc_ex.h1889 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1891 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1912 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
1955 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1957 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
1968 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
2462 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
2466 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
2487 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
2490 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Dstm32f3xx_ll_bus.h75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h989 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
991 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
995 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
1532 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
1533 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Dstm32f0xx_ll_bus.h75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h629 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
631 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
635 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
740 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
741 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Dstm32f1xx_ll_bus.h79 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
712 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
760 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
1238 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != 0U)
1256 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == 0U)
Dstm32u0xx_ll_bus.h83 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h870 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
872 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \
917 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN)
1465 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET)
1478 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET)
Dstm32g0xx_ll_bus.h75 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f100xe.h1526 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32f101xg.h1548 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32f101xe.h1505 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h4395 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l151xc.h4454 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l151xca.h4482 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l151xdx.h4535 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l151xe.h4535 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l152xc.h4569 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l152xca.h4618 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l152xdx.h4671 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l152xe.h4671 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro
Dstm32l162xc.h4702 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enab… macro

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