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Searched refs:RCC_AHBENR_DMA1EN (Results 1 – 25 of 119) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h323 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
325 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
353 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
370 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
371 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Dstm32f1xx_ll_bus.h77 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h678 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
680 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
701 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
798 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
801 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
Dstm32l0xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h657 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
659 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
682 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
701 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
709 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Dstm32f0xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h724 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
726 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
757 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
906 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
917 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
Dstm32f3xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h692 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
694 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
706 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
1119 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U)
1127 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U)
Dstm32l1xx_ll_bus.h90 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h698 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
700 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
721 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
1017 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
1021 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
Dstm32c0xx_ll_bus.h75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h702 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
704 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
758 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
1235 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != 0U)
1253 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == 0U)
Dstm32u0xx_ll_bus.h81 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h861 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
863 … tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \
915 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
1463 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
1476 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET)
Dstm32g0xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h1106 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enab… macro
Dstm32f101xb.h1136 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enab… macro
Dstm32f100xb.h1217 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enab… macro
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3077 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro
Dstm32f030x8.h3106 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro
Dstm32f070x6.h3143 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h3762 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro
Dstm32l010x8.h3464 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro
Dstm32l010xb.h3483 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ macro

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