Home
last modified time | relevance | path

Searched refs:RCC_AHB1ENR_FLASHEN (Results 1 – 25 of 67) sorted by relevance

123

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc.h578 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
580 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
629 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
1079 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
Dstm32wbaxx_ll_bus.h74 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h558 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
560 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
582 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
1253 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
1267 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
Dstm32g4xx_ll_bus.h78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
679 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
714 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
1372 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
1387 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
Dstm32l5xx_ll_bus.h74 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
667 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
716 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
1654 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
1677 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
Dstm32l4xx_ll_bus.h78 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_rcc.h730 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
732 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
824 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
1996 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
2040 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
Dstm32u5xx_ll_bus.h77 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6223 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32wba52xx.h10020 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h7552 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g411xc.h7723 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g441xx.h7927 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32gbk1cb.h7686 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g431xx.h7703 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g4a1xx.h8300 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g491xx.h8076 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g473xx.h8757 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32g471xx.h8231 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h6092 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32l412xx.h5873 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32l433xx.h9849 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro
Dstm32l451xx.h10010 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk macro

123