Searched refs:RAMCFG_ICR_CDED_Pos (Results 1 – 22 of 22) sorted by relevance
8159 #define RAMCFG_ICR_CDED_Pos (1U) macro8160 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
12098 #define RAMCFG_ICR_CDED_Pos (1U) macro12099 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
12827 #define RAMCFG_ICR_CDED_Pos (1U) macro12828 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
12617 #define RAMCFG_ICR_CDED_Pos (1U) macro12618 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
15430 #define RAMCFG_ICR_CDED_Pos (1U) macro15431 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
14911 #define RAMCFG_ICR_CDED_Pos (1U) macro14912 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
13950 #define RAMCFG_ICR_CDED_Pos (1U) macro13951 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
13437 #define RAMCFG_ICR_CDED_Pos (1U) macro13438 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
14845 #define RAMCFG_ICR_CDED_Pos (1U) macro14846 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
15407 #define RAMCFG_ICR_CDED_Pos (1U) macro15408 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
15873 #define RAMCFG_ICR_CDED_Pos (1U) macro15874 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
16435 #define RAMCFG_ICR_CDED_Pos (1U) macro16436 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
17399 #define RAMCFG_ICR_CDED_Pos (1U) macro17400 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
19592 #define RAMCFG_ICR_CDED_Pos (1U) macro19593 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
17961 #define RAMCFG_ICR_CDED_Pos (1U) macro17962 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
20528 #define RAMCFG_ICR_CDED_Pos (1U) macro20529 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
20154 #define RAMCFG_ICR_CDED_Pos (1U) macro20155 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
21090 #define RAMCFG_ICR_CDED_Pos (1U) macro21091 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002…
25045 #define RAMCFG_ICR_CDED_Pos (1U) macro25046 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */
26194 #define RAMCFG_ICR_CDED_Pos (1U) macro26195 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */
25952 #define RAMCFG_ICR_CDED_Pos (1U) macro25953 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */
25287 #define RAMCFG_ICR_CDED_Pos (1U) macro25288 #define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */