Home
last modified time | relevance | path

Searched refs:QUADSPI_DCR_CKMODE_Pos (Results 1 – 25 of 83) sorted by relevance

1234

/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h7589 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7590 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l412xx.h7364 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7365 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l433xx.h12054 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
12055 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l451xx.h12109 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
12110 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l442xx.h11284 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
11285 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l431xx.h11825 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
11826 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32l432xx.h11059 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
11060 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb35xx.h6946 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
6947 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32wb55xx.h7137 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7138 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32wb5mxx.h7137 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7138 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g4a1xx.h7661 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7662 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32g491xx.h7440 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7441 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32g473xx.h8103 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
8104 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32g471xx.h7589 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
7590 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32g483xx.h8324 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
8325 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h8943 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
8944 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f722xx.h8927 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
8928 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f730xx.h9157 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9158 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f733xx.h9157 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9158 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f732xx.h9141 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9142 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h9323 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9324 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f412zx.h9053 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9054 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f412rx.h9047 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9048 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f412vx.h9049 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9050 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
Dstm32f413xx.h9287 #define QUADSPI_DCR_CKMODE_Pos (0U) macro
9288 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */

1234