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Searched refs:PWR_SVMSR_REGS_Pos (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba5mxx.h9354 #define PWR_SVMSR_REGS_Pos (1U) macro
9355 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32wba55xx.h9354 #define PWR_SVMSR_REGS_Pos (1U) macro
9355 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h13190 #define PWR_SVMSR_REGS_Pos (1U) macro
13191 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u535xx.h12677 #define PWR_SVMSR_REGS_Pos (1U) macro
12678 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u575xx.h13846 #define PWR_SVMSR_REGS_Pos (1U) macro
13847 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u585xx.h14408 #define PWR_SVMSR_REGS_Pos (1U) macro
14409 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u595xx.h14668 #define PWR_SVMSR_REGS_Pos (1U) macro
14669 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5a5xx.h15230 #define PWR_SVMSR_REGS_Pos (1U) macro
15231 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5f7xx.h16169 #define PWR_SVMSR_REGS_Pos (1U) macro
16170 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u599xx.h18387 #define PWR_SVMSR_REGS_Pos (1U) macro
18388 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5g7xx.h16731 #define PWR_SVMSR_REGS_Pos (1U) macro
16732 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5f9xx.h19298 #define PWR_SVMSR_REGS_Pos (1U) macro
19299 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5a9xx.h18949 #define PWR_SVMSR_REGS_Pos (1U) macro
18950 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…
Dstm32u5g9xx.h19860 #define PWR_SVMSR_REGS_Pos (1U) macro
19861 #define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002…