Home
last modified time | relevance | path

Searched refs:PWR_CR2_SRAM2PDS1_Pos (Results 1 – 18 of 18) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_pwr_ex.c1790 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); in HAL_PWREx_EnableRAMsContentStopRetention()
2040 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); in HAL_PWREx_DisableRAMsContentStopRetention()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h5289 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
5290 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32wba52xx.h8890 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
8891 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32wba54xx.h9160 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
9161 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32wba5mxx.h9160 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
9161 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32wba55xx.h9160 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
9161 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12929 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
12930 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u535xx.h12419 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
12420 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u575xx.h13554 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
13555 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u585xx.h14113 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
14114 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u595xx.h14355 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
14356 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5a5xx.h14914 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
14915 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5f7xx.h15856 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
15857 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u599xx.h18074 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
18075 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5g7xx.h16415 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
16416 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5f9xx.h18982 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
18983 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5a9xx.h18633 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
18634 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…
Dstm32u5g9xx.h19541 #define PWR_CR2_SRAM2PDS1_Pos (4U) macro
19542 #define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010…