Home
last modified time | relevance | path

Searched refs:OCNIdleState (Results 1 – 25 of 109) sorted by relevance

12345

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c361 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
811 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
823 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
890 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
902 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
969 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
981 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1048 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1060 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1119 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c402 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
852 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
864 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
931 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
943 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1010 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1022 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1089 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1101 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1160 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c398 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
848 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
860 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
927 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
939 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1006 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1018 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1085 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1097 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1156 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
Dstm32u5xx_hal_tim.c4503 temp1.OCNIdleState = sConfig->OCNIdleState; in HAL_TIM_OnePulse_ConfigChannel()
7357 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC1_SetConfig()
7366 tmpcr2 |= OC_Config->OCNIdleState; in TIM_OC1_SetConfig()
7433 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC2_SetConfig()
7442 tmpcr2 |= (OC_Config->OCNIdleState << 2U); in TIM_OC2_SetConfig()
7508 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC3_SetConfig()
7517 tmpcr2 |= (OC_Config->OCNIdleState << 4U); in TIM_OC3_SetConfig()
7584 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC4_SetConfig()
7595 tmpcr2 |= (OC_Config->OCNIdleState << 6U); in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c439 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
889 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
901 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
968 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
980 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1047 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1059 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1126 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1138 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1197 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
Dstm32n6xx_hal_tim.c4495 temp1.OCNIdleState = sConfig->OCNIdleState; in HAL_TIM_OnePulse_ConfigChannel()
7333 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC1_SetConfig()
7342 tmpcr2 |= OC_Config->OCNIdleState; in TIM_OC1_SetConfig()
7409 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC2_SetConfig()
7418 tmpcr2 |= (OC_Config->OCNIdleState << 2U); in TIM_OC2_SetConfig()
7484 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC3_SetConfig()
7493 tmpcr2 |= (OC_Config->OCNIdleState << 4U); in TIM_OC3_SetConfig()
7560 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC4_SetConfig()
7571 tmpcr2 |= (OC_Config->OCNIdleState << 6U); in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c396 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
846 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
858 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
925 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
937 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1004 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1016 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1083 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1095 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1154 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c433 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
883 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
895 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
962 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
974 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1041 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1053 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1132 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); in OC4Config()
1191 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
[all …]
Dstm32h5xx_hal_tim.c4503 temp1.OCNIdleState = sConfig->OCNIdleState; in HAL_TIM_OnePulse_ConfigChannel()
7366 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC1_SetConfig()
7375 tmpcr2 |= OC_Config->OCNIdleState; in TIM_OC1_SetConfig()
7442 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC2_SetConfig()
7451 tmpcr2 |= (OC_Config->OCNIdleState << 2U); in TIM_OC2_SetConfig()
7517 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC3_SetConfig()
7526 tmpcr2 |= (OC_Config->OCNIdleState << 4U); in TIM_OC3_SetConfig()
7593 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); in TIM_OC4_SetConfig()
7604 tmpcr2 |= (OC_Config->OCNIdleState << 6U); in TIM_OC4_SetConfig()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c344 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
794 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
873 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
886 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
952 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
965 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1031 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1094 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1155 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c420 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
864 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
877 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
943 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
956 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1022 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1035 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1101 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC4Config()
1164 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1225 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_tim.c355 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
717 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
730 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
798 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
810 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
879 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
891 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1021 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1084 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c412 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
856 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
868 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
935 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
947 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1014 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1026 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1152 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1213 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_ll_tim.c365 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
815 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
827 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
894 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
906 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
973 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
985 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1111 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1172 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c356 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
806 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
818 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
885 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
897 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
964 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
976 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1102 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1163 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c348 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
798 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
810 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
877 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
889 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
956 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
968 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1094 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1155 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c379 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
829 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
841 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
908 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
920 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
987 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
999 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1125 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1186 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c385 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
829 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
841 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
908 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
920 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
987 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
999 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1125 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1186 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c388 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
838 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
850 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
917 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
929 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1008 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1134 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1195 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c456 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
917 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
929 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
1010 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1078 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1092 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1224 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1288 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c424 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
886 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
898 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
965 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
977 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
1044 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
1056 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
1182 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC5Config()
1243 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC6Config()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c366 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
781 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
793 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
860 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
872 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
939 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
951 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c366 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
781 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
793 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
860 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
872 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
939 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
951 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c345 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
760 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
772 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
839 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
851 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
918 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
930 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c386 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
799 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC1Config()
811 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); in OC1Config()
878 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC2Config()
890 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); in OC2Config()
957 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); in OC3Config()
969 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); in OC3Config()

12345