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Searched refs:OCIdleState (Results 1 – 25 of 109) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_tim.c354 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
718 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
727 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
795 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
876 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
888 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
957 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
960 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1022 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c411 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
853 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
865 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
932 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
944 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1011 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1023 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1090 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1093 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1153 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_ll_tim.c364 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
812 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
824 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
891 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
903 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
970 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
982 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1049 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1052 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1112 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
Dstm32u0xx_hal_tim.c4446 temp1.OCIdleState = sConfig->OCIdleState; in HAL_TIM_OnePulse_ConfigChannel()
7059 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC1_SetConfig()
7065 tmpcr2 |= OC_Config->OCIdleState; in TIM_OC1_SetConfig()
7135 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC2_SetConfig()
7141 tmpcr2 |= (OC_Config->OCIdleState << 2U); in TIM_OC2_SetConfig()
7210 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC3_SetConfig()
7216 tmpcr2 |= (OC_Config->OCIdleState << 4U); in TIM_OC3_SetConfig()
7273 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC4_SetConfig()
7279 tmpcr2 |= (OC_Config->OCIdleState << 6U); in TIM_OC4_SetConfig()
7334 tmpcr2 |= (OC_Config->OCIdleState << 8U); in TIM_OC5_SetConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c343 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
795 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
804 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
874 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
883 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
953 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
962 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1032 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1035 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1095 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c360 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
808 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
820 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
887 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
899 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
966 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
978 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1045 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1057 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c355 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
803 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
815 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
882 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
894 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
961 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
973 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1040 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1043 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1103 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c347 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
795 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
807 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
874 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
886 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
953 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
965 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1032 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1035 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1095 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c378 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
826 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
838 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
905 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
917 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
984 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
996 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1063 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1066 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1126 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c384 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
826 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
838 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
905 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
917 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
984 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
996 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1063 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1066 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1126 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c387 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
835 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
847 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
914 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
926 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
993 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1005 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1072 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1075 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1135 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_tim.c401 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
849 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
861 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
928 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
940 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1007 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1019 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1086 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1098 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1161 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c455 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
914 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
926 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
993 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
1005 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1075 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1089 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1157 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1162 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1225 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
Dstm32f3xx_hal_tim.c4457 temp1.OCIdleState = sConfig->OCIdleState; in HAL_TIM_OnePulse_ConfigChannel()
7072 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC1_SetConfig()
7078 tmpcr2 |= OC_Config->OCIdleState; in TIM_OC1_SetConfig()
7148 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC2_SetConfig()
7156 tmpcr2 |= (OC_Config->OCIdleState << 2U); in TIM_OC2_SetConfig()
7226 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC3_SetConfig()
7232 tmpcr2 |= (OC_Config->OCIdleState << 4U); in TIM_OC3_SetConfig()
7291 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC4_SetConfig()
7297 tmpcr2 |= (OC_Config->OCIdleState << 6U); in TIM_OC4_SetConfig()
7354 tmpcr2 |= (OC_Config->OCIdleState << 8U); in TIM_OC5_SetConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c397 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
845 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
857 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
924 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
936 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1003 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1015 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1082 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1094 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1157 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c419 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
865 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
874 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
944 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
953 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1023 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1032 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1102 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1105 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1165 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
Dstm32mp1xx_hal_tim.c3777 temp1.OCIdleState = sConfig->OCIdleState; in HAL_TIM_OnePulse_ConfigChannel()
6039 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC1_SetConfig()
6045 tmpcr2 |= OC_Config->OCIdleState; in TIM_OC1_SetConfig()
6115 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC2_SetConfig()
6121 tmpcr2 |= (OC_Config->OCIdleState << 2U); in TIM_OC2_SetConfig()
6189 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC3_SetConfig()
6195 tmpcr2 |= (OC_Config->OCIdleState << 4U); in TIM_OC3_SetConfig()
6251 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); in TIM_OC4_SetConfig()
6257 tmpcr2 |= (OC_Config->OCIdleState << 6U); in TIM_OC4_SetConfig()
6311 tmpcr2 |= (OC_Config->OCIdleState << 8U); in TIM_OC5_SetConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_ll_tim.c438 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
886 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
898 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
965 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
977 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1044 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1056 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1123 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1135 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1198 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c423 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
883 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
895 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
962 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
974 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1041 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1053 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1123 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1183 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c395 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
843 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
855 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
922 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
934 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1001 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1013 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1080 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1092 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1155 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c432 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
880 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
892 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
959 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
971 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
1038 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
1050 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1117 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1129 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
1192 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC5Config()
[all …]
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c365 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
778 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
790 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
857 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
869 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
936 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
948 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1015 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1018 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c365 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
778 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
790 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
857 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
869 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
936 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
948 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1015 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1018 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c344 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
757 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
769 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
836 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
848 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
915 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
927 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
994 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
997 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c385 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; in LL_TIM_OC_StructInit()
796 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC1Config()
808 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); in OC1Config()
875 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC2Config()
887 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); in OC2Config()
954 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC3Config()
966 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); in OC3Config()
1033 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); in OC4Config()
1036 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); in OC4Config()

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