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Searched refs:LPTIM_CFGR2_IN2SEL_Pos (Results 1 – 25 of 88) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h7024 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7025 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
7027 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
7028 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
7029 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
7030 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g041xx.h7328 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7329 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
7331 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
7332 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
7333 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
7334 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g051xx.h7442 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7443 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
7445 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
7446 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
7447 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
7448 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g061xx.h7746 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7747 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
7749 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
7750 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
7751 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
7752 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g071xx.h7826 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7827 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
7829 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
7830 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
7831 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
7832 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g081xx.h8130 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8131 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
8133 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
8134 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
8135 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
8136 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g0c1xx.h9714 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
9715 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
9717 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
9718 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
9719 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
9720 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
Dstm32g0b1xx.h9410 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
9411 #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
9413 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
9414 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
9415 #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
9416 #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h4875 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
4876 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
4878 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
4879 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32wba52xx.h8476 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8477 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
8479 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
8480 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32wba54xx.h8710 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8711 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
8713 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
8714 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32wba5mxx.h8710 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8711 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
8713 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
8714 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32wba55xx.h8710 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8711 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
8713 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
8714 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8241 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8242 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
8244 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
8245 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
Dstm32u083xx.h9178 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
9179 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
9181 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
9182 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
Dstm32u073xx.h8908 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
8909 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
8911 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
8912 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7790 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
7791 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
7793 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
7794 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32h523xx.h10229 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
10230 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
10232 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
10233 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
Dstm32h562xx.h10955 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
10956 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
10958 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
10959 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h18709 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
18710 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
18712 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
18713 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
Dstm32h7b0xx.h19189 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
19190 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
19192 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
19193 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
Dstm32h7b0xxq.h19201 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
19202 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
19204 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
19205 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
Dstm32h7a3xxq.h18721 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
18722 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
18724 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
18725 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11321 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
11322 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030…
11324 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010…
11325 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h12724 #define LPTIM_CFGR2_IN2SEL_Pos (4U) macro
12725 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
12727 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
12728 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */

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