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Searched refs:LPTIM_CFGR2_IC2SEL_Pos (Results 1 – 25 of 34) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h4885 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
4886 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
4888 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
4889 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32wba52xx.h8486 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8487 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
8489 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
8490 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32wba54xx.h8720 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8721 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
8723 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
8724 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32wba5mxx.h8720 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8721 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
8723 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
8724 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32wba55xx.h8720 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8721 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
8723 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
8724 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h8251 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8252 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00300000 */
8254 #define LPTIM_CFGR2_IC2SEL_0 (0x1U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
8255 #define LPTIM_CFGR2_IC2SEL_1 (0x2U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
Dstm32u083xx.h9188 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
9189 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00300000 */
9191 #define LPTIM_CFGR2_IC2SEL_0 (0x1U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
9192 #define LPTIM_CFGR2_IC2SEL_1 (0x2U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
Dstm32u073xx.h8918 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
8919 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00300000 */
8921 #define LPTIM_CFGR2_IC2SEL_0 (0x1U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
8922 #define LPTIM_CFGR2_IC2SEL_1 (0x2U << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7800 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
7801 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
7803 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
7804 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32h523xx.h10239 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
10240 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
10242 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
10243 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32h562xx.h10965 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
10966 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
10968 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
10969 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32h533xx.h10648 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
10649 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
10651 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
10652 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32h573xx.h13458 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
13459 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
13461 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
13462 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32h563xx.h13049 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
13050 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
13052 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
13053 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11331 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
11332 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
11334 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
11335 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u535xx.h10931 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
10932 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
10934 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
10935 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u575xx.h11966 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
11967 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
11969 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
11970 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u585xx.h12415 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
12416 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
12418 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
12419 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u595xx.h12276 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
12277 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
12279 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
12280 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u5a5xx.h12725 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
12726 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
12728 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
12729 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
Dstm32u5f7xx.h13774 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
13775 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030…
13777 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000…
13778 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h12734 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
12735 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030 */
12737 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
12738 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
Dstm32h7s7xx.h13323 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
13324 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030 */
13326 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
13327 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
Dstm32h7s3xx.h13179 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
13180 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030 */
13182 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
13183 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
Dstm32h7r7xx.h12876 #define LPTIM_CFGR2_IC2SEL_Pos (20U) macro
12877 #define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030 */
12879 #define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
12880 #define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */

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