Home
last modified time | relevance | path

Searched refs:Instance (Results 1 – 25 of 2050) sorted by relevance

12345678910>>...82

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_dma.h138 …void *Instance; … member
690 …NDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->I…
698 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)-…
699 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
707 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)-…
708 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
719 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
720 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
402 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
403 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; in HAL_DSI_Init()
407 hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; in HAL_DSI_Init()
409 hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; in HAL_DSI_Init()
413 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
414 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
[all …]
Dstm32h7xx_hal_adc.c423 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
486 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
489 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
496 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
499 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
514 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
529 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
545 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
547 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) in HAL_ADC_Init()
566 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); in HAL_ADC_Init()
[all …]
Dstm32h7xx_hal_adc_ex.c132 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_Start()
152 LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); in HAL_ADCEx_Calibration_Start()
155 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) in HAL_ADCEx_Calibration_Start()
203 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_GetValue()
207 return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); in HAL_ADCEx_Calibration_GetValue()
223 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_LinearCalibration_GetValue()
226 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
233 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) in HAL_ADCEx_LinearCalibration_GetValue()
235 LL_ADC_REG_StopConversion(hadc->Instance); in HAL_ADCEx_LinearCalibration_GetValue()
240 …LinearCalib_Buffer[cnt - 1U] = LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW… in HAL_ADCEx_LinearCalibration_GetValue()
[all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
402 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
403 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; in HAL_DSI_Init()
407 hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; in HAL_DSI_Init()
409 hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; in HAL_DSI_Init()
413 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
414 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
[all …]
Dstm32f4xx_hal_cryp.c322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR…
323 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_…
330 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_Init()
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_Init()
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_SetConfig()
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_SetConfig()
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); in HAL_CRYP_Encrypt()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
402 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
403 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; in HAL_DSI_Init()
407 hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; in HAL_DSI_Init()
409 hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; in HAL_DSI_Init()
413 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
414 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
[all …]
Dstm32f7xx_hal_cryp.c322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR…
323 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_…
330 … (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_Init()
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_Init()
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, in HAL_CRYP_SetConfig()
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, in HAL_CRYP_SetConfig()
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); in HAL_CRYP_Encrypt()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_dsi.c260 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
271 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
373 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); in HAL_DSI_Init()
374 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ in HAL_DSI_Init()
402 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; in HAL_DSI_Init()
403 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; in HAL_DSI_Init()
407 hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; in HAL_DSI_Init()
409 hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; in HAL_DSI_Init()
413 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; in HAL_DSI_Init()
414 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; in HAL_DSI_Init()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dsi.c263 while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) in DSI_ShortWrite()
274 hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); in DSI_ShortWrite()
289 hdsi->Instance->DPCBCR &= ~DSI_DPCBCR; in DSI_ConfigBandControl()
290 hdsi->Instance->DPCBCR |= (hdsi->Init.PHYFrequencyRange << DSI_DPCBCR_Pos); in DSI_ConfigBandControl()
293 hdsi->Instance->DPCSRCR = DSI_DPHY_SLEW_HS_TX_SPEED; in DSI_ConfigBandControl()
296 hdsi->Instance->DPDL0BCR &= ~DSI_DPDL0BCR; in DSI_ConfigBandControl()
297 hdsi->Instance->DPDL0BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL0BCR_Pos); in DSI_ConfigBandControl()
300 hdsi->Instance->DPDL0SRCR = DSI_DPHY_SLEW_HS_TX_SPEED; in DSI_ConfigBandControl()
303 hdsi->Instance->DPDL1BCR &= ~DSI_DPDL1BCR; in DSI_ConfigBandControl()
304 hdsi->Instance->DPDL1BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL1BCR_Pos); in DSI_ConfigBandControl()
[all …]
Dstm32u5xx_hal_mdf.c312 assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); in HAL_MDF_Init()
317 if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL) in HAL_MDF_Init()
325 if (IS_ADF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
353 if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) || in HAL_MDF_Init()
354 ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance))) in HAL_MDF_Init()
358 mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; in HAL_MDF_Init()
368 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
391 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
415 if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) in HAL_MDF_Init()
425 hmdf->Instance->SITFCR = 0U; in HAL_MDF_Init()
[all …]
Dstm32u5xx_hal_adc.c423 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADC_Init()
429 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
456 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
486 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */ in HAL_ADC_Init()
518 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) in HAL_ADC_Init()
521 LL_ADC_DisableDeepPowerDown(hadc->Instance); in HAL_ADC_Init()
528 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
531 LL_ADC_EnableInternalRegulator(hadc->Instance); in HAL_ADC_Init()
546 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) in HAL_ADC_Init()
561 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); in HAL_ADC_Init()
[all …]
Dstm32u5xx_hal_pka.c374 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
404 while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) in HAL_PKA_Init()
406 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
427 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
456 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
463 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
466 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
530 while (hpka->Instance->CR != PKA_CR_EN) in HAL_PKA_MspDeInit()
532 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_MspDeInit()
553 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_MspDeInit()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_opamp_ex.c109 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
110 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
114 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
115 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
118 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM); in HAL_OPAMPEx_SelfCalibrateAll()
119 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM); in HAL_OPAMPEx_SelfCalibrateAll()
122 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON); in HAL_OPAMPEx_SelfCalibrateAll()
123 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON); in HAL_OPAMPEx_SelfCalibrateAll()
127 MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); in HAL_OPAMPEx_SelfCalibrateAll()
128 MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_opamp_ex.c179 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
183 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
184 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
188 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
189 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
190 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
192 assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); in HAL_OPAMPEx_SelfCalibrateAll()
197 SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
201 SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
202 SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP); in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_cryp.c335 …P_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \
341 …S_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
346 #define CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_FFL…
350 … SET_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
352 … tmpreg = READ_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
354 … CLEAR_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
463 if (IS_SAES_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
470 if (IS_CRYP_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
479 if (IS_CRYP_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
491 if (IS_SAES_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
[all …]
Dstm32n6xx_hal_mdf.c308 assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); in HAL_MDF_Init()
313 if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL) in HAL_MDF_Init()
321 if (IS_ADF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
349 if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) || in HAL_MDF_Init()
350 ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance))) in HAL_MDF_Init()
354 mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; in HAL_MDF_Init()
364 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
387 if (IS_MDF_INSTANCE(hmdf->Instance)) in HAL_MDF_Init()
411 if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) in HAL_MDF_Init()
421 hmdf->Instance->SITFCR = 0U; in HAL_MDF_Init()
[all …]
Dstm32n6xx_hal_eth_ex.c142 SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); in HAL_ETHEx_EnableARPOffload()
153 CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); in HAL_ETHEx_DisableARPOffload()
165 WRITE_REG(heth->Instance->MACARPAR, IpAddress); in HAL_ETHEx_SetARPAddressMatch()
192 MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | in HAL_ETHEx_SetL4FilterConfig()
197 …WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
203 MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | in HAL_ETHEx_SetL4FilterConfig()
208 …WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
212 SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); in HAL_ETHEx_SetL4FilterConfig()
241 pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4C0R_L4PEN0); in HAL_ETHEx_GetL4FilterConfig()
242 pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R, in HAL_ETHEx_GetL4FilterConfig()
[all …]
Dstm32n6xx_hal_pka.c376 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
403 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
415 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
444 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
451 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
454 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
924 PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); in HAL_PKA_ModExp_GetResult()
979 PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); in HAL_PKA_ECDSASign_GetResult()
980 PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); in HAL_PKA_ECDSASign_GetResult()
987 PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); in HAL_PKA_ECDSASign_GetResult()
[all …]
Dstm32n6xx_hal_adc_ex.c143 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); in HAL_ADCEx_Calibration_Start()
153 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) in HAL_ADCEx_Calibration_Start()
162 backup_trigger_settings = READ_REG(hadc->Instance->CFGR1); in HAL_ADCEx_Calibration_Start()
163 backup_offset_config[0] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1); in HAL_ADCEx_Calibration_Start()
164 backup_offset_config[1] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2); in HAL_ADCEx_Calibration_Start()
165 backup_offset_config[2] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_3); in HAL_ADCEx_Calibration_Start()
166 backup_offset_config[3] = LL_ADC_GetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_4); in HAL_ADCEx_Calibration_Start()
169 …CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT | ADC_CFGR1_EXTEN | ADC_CFGR1_CONT | ADC_CFGR1_RE… in HAL_ADCEx_Calibration_Start()
170 LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_1, 0); in HAL_ADCEx_Calibration_Start()
171 LL_ADC_SetOffsetLevel(hadc->Instance, LL_ADC_OFFSET_2, 0); in HAL_ADCEx_Calibration_Start()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_cryp.c335 …P_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \
341 …S_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
346 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR…
454 if (IS_SAES_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
461 if (IS_CRYP_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
470 if (IS_CRYP_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
482 if (IS_SAES_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
525 if (IS_CRYP_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
527 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, in HAL_CRYP_Init()
533 if (IS_SAES_INSTANCE(hcryp->Instance)) in HAL_CRYP_Init()
[all …]
Dstm32h7rsxx_hal_pka.c377 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
407 while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) in HAL_PKA_Init()
409 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
430 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
459 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
466 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
469 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
533 while (hpka->Instance->CR != PKA_CR_EN) in HAL_PKA_MspDeInit()
535 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_MspDeInit()
556 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_MspDeInit()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_pka.c374 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
404 while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) in HAL_PKA_Init()
406 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
427 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
456 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
463 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
466 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
530 while (hpka->Instance->CR != PKA_CR_EN) in HAL_PKA_MspDeInit()
532 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_MspDeInit()
553 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_MspDeInit()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_pka.c374 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
404 while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) in HAL_PKA_Init()
406 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
427 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_Init()
456 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
463 hpka->Instance->CR = 0; in HAL_PKA_DeInit()
466 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_DeInit()
530 while (hpka->Instance->CR != PKA_CR_EN) in HAL_PKA_MspDeInit()
532 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_MspDeInit()
553 …SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PK… in HAL_PKA_MspDeInit()
[all …]
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_hal_pka.c390 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_Init()
421 SET_BIT(hpka->Instance->CSR, PKA_CSR_SFT_RST); in HAL_PKA_Init()
422 CLEAR_BIT(hpka->Instance->CSR, PKA_CSR_SFT_RST); in HAL_PKA_Init()
426 while ((hpka->Instance->CR & PKA_CR_EN) != PKA_CR_EN) in HAL_PKA_Init()
428 hpka->Instance->CR = PKA_CR_EN; in HAL_PKA_Init()
441 … SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC); in HAL_PKA_Init()
460 SET_BIT(hpka->Instance->ISR, PKA_ISR_PROC_END | PKA_ISR_RAM_ERR | PKA_ISR_ADD_ERR); in HAL_PKA_Init()
461 CLEAR_BIT(hpka->Instance->ISR, PKA_ISR_PROC_END | PKA_ISR_RAM_ERR | PKA_ISR_ADD_ERR); in HAL_PKA_Init()
491 assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); in HAL_PKA_DeInit()
498 SET_BIT(hpka->Instance->CSR, PKA_CSR_SFT_RST); in HAL_PKA_DeInit()
[all …]

12345678910>>...82