260   while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)  in DSI_ShortWrite()
271   hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));  in DSI_ShortWrite()
373   hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);  in HAL_DSI_Init()
374   hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \  in HAL_DSI_Init()
402   hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;  in HAL_DSI_Init()
403   hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;  in HAL_DSI_Init()
407   hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;  in HAL_DSI_Init()
409   hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;  in HAL_DSI_Init()
413   hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;  in HAL_DSI_Init()
414   hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;  in HAL_DSI_Init()
418   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_Init()
420     while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))  in HAL_DSI_Init()
433     while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \  in HAL_DSI_Init()
453   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;  in HAL_DSI_Init()
454   hdsi->Instance->WPCR[0U] |= unitIntervalx4;  in HAL_DSI_Init()
459   hdsi->Instance->IER[0U] = 0U;  in HAL_DSI_Init()
460   hdsi->Instance->IER[1U] = 0U;  in HAL_DSI_Init()
466   hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);  in HAL_DSI_Init()
467   hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);  in HAL_DSI_Init()
503   hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);  in HAL_DSI_DeInit()
548   hdsi->Instance->IER[0U] = 0U;  in HAL_DSI_ConfigErrorMonitor()
549   hdsi->Instance->IER[1U] = 0U;  in HAL_DSI_ConfigErrorMonitor()
557     hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;  in HAL_DSI_ConfigErrorMonitor()
563     hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;  in HAL_DSI_ConfigErrorMonitor()
569     hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;  in HAL_DSI_ConfigErrorMonitor()
575     hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;  in HAL_DSI_ConfigErrorMonitor()
581     hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;  in HAL_DSI_ConfigErrorMonitor()
587     hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;  in HAL_DSI_ConfigErrorMonitor()
593     hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;  in HAL_DSI_ConfigErrorMonitor()
599     hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;  in HAL_DSI_ConfigErrorMonitor()
605     hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;  in HAL_DSI_ConfigErrorMonitor()
611     hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;  in HAL_DSI_ConfigErrorMonitor()
902     ErrorStatus0 = hdsi->Instance->ISR[0U];  in HAL_DSI_IRQHandler()
903     ErrorStatus0 &= hdsi->Instance->IER[0U];  in HAL_DSI_IRQHandler()
904     ErrorStatus1 = hdsi->Instance->ISR[1U];  in HAL_DSI_IRQHandler()
905     ErrorStatus1 &= hdsi->Instance->IER[1U];  in HAL_DSI_IRQHandler()
1074   hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;  in HAL_DSI_SetGenericVCID()
1075   hdsi->Instance->GVCIDR |= VirtualChannelID;  in HAL_DSI_SetGenericVCID()
1117   hdsi->Instance->MCR &= ~DSI_MCR_CMDM;  in HAL_DSI_ConfigVideoMode()
1118   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;  in HAL_DSI_ConfigVideoMode()
1121   hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;  in HAL_DSI_ConfigVideoMode()
1122   hdsi->Instance->VMCR |= VidCfg->Mode;  in HAL_DSI_ConfigVideoMode()
1125   hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;  in HAL_DSI_ConfigVideoMode()
1126   hdsi->Instance->VPCR |= VidCfg->PacketSize;  in HAL_DSI_ConfigVideoMode()
1129   hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;  in HAL_DSI_ConfigVideoMode()
1130   hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;  in HAL_DSI_ConfigVideoMode()
1133   hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;  in HAL_DSI_ConfigVideoMode()
1134   hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;  in HAL_DSI_ConfigVideoMode()
1137   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;  in HAL_DSI_ConfigVideoMode()
1138   hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;  in HAL_DSI_ConfigVideoMode()
1141   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);  in HAL_DSI_ConfigVideoMode()
1142   hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);  in HAL_DSI_ConfigVideoMode()
1145   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;  in HAL_DSI_ConfigVideoMode()
1146   hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;  in HAL_DSI_ConfigVideoMode()
1149   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;  in HAL_DSI_ConfigVideoMode()
1150   hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);  in HAL_DSI_ConfigVideoMode()
1155     hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;  in HAL_DSI_ConfigVideoMode()
1156     hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;  in HAL_DSI_ConfigVideoMode()
1160   hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;  in HAL_DSI_ConfigVideoMode()
1161   hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;  in HAL_DSI_ConfigVideoMode()
1164   hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;  in HAL_DSI_ConfigVideoMode()
1165   hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;  in HAL_DSI_ConfigVideoMode()
1168   hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;  in HAL_DSI_ConfigVideoMode()
1169   hdsi->Instance->VLCR |= VidCfg->HorizontalLine;  in HAL_DSI_ConfigVideoMode()
1172   hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;  in HAL_DSI_ConfigVideoMode()
1173   hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;  in HAL_DSI_ConfigVideoMode()
1176   hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;  in HAL_DSI_ConfigVideoMode()
1177   hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;  in HAL_DSI_ConfigVideoMode()
1180   hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;  in HAL_DSI_ConfigVideoMode()
1181   hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;  in HAL_DSI_ConfigVideoMode()
1184   hdsi->Instance->VVACR &= ~DSI_VVACR_VA;  in HAL_DSI_ConfigVideoMode()
1185   hdsi->Instance->VVACR |= VidCfg->VerticalActive;  in HAL_DSI_ConfigVideoMode()
1188   hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;  in HAL_DSI_ConfigVideoMode()
1189   hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;  in HAL_DSI_ConfigVideoMode()
1192   hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;  in HAL_DSI_ConfigVideoMode()
1193   hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);  in HAL_DSI_ConfigVideoMode()
1196   hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;  in HAL_DSI_ConfigVideoMode()
1197   hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;  in HAL_DSI_ConfigVideoMode()
1200   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;  in HAL_DSI_ConfigVideoMode()
1201   hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;  in HAL_DSI_ConfigVideoMode()
1204   hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;  in HAL_DSI_ConfigVideoMode()
1205   hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;  in HAL_DSI_ConfigVideoMode()
1208   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;  in HAL_DSI_ConfigVideoMode()
1209   hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;  in HAL_DSI_ConfigVideoMode()
1212   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;  in HAL_DSI_ConfigVideoMode()
1213   hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;  in HAL_DSI_ConfigVideoMode()
1216   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;  in HAL_DSI_ConfigVideoMode()
1217   hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;  in HAL_DSI_ConfigVideoMode()
1220   hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;  in HAL_DSI_ConfigVideoMode()
1221   hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;  in HAL_DSI_ConfigVideoMode()
1224   hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;  in HAL_DSI_ConfigVideoMode()
1225   hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;  in HAL_DSI_ConfigVideoMode()
1258   hdsi->Instance->MCR |= DSI_MCR_CMDM;  in HAL_DSI_ConfigAdaptedCommandMode()
1259   hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;  in HAL_DSI_ConfigAdaptedCommandMode()
1260   hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;  in HAL_DSI_ConfigAdaptedCommandMode()
1263   hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;  in HAL_DSI_ConfigAdaptedCommandMode()
1264   hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;  in HAL_DSI_ConfigAdaptedCommandMode()
1267   hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);  in HAL_DSI_ConfigAdaptedCommandMode()
1268   hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);  in HAL_DSI_ConfigAdaptedCommandMode()
1271   hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;  in HAL_DSI_ConfigAdaptedCommandMode()
1272   hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;  in HAL_DSI_ConfigAdaptedCommandMode()
1275   hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;  in HAL_DSI_ConfigAdaptedCommandMode()
1276   hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);  in HAL_DSI_ConfigAdaptedCommandMode()
1279   hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;  in HAL_DSI_ConfigAdaptedCommandMode()
1280   hdsi->Instance->LCCR |= CmdCfg->CommandSize;  in HAL_DSI_ConfigAdaptedCommandMode()
1283   hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);  in HAL_DSI_ConfigAdaptedCommandMode()
1284 …hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->Au…  in HAL_DSI_ConfigAdaptedCommandMode()
1288   hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;  in HAL_DSI_ConfigAdaptedCommandMode()
1289   hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;  in HAL_DSI_ConfigAdaptedCommandMode()
1332   hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \  in HAL_DSI_ConfigCommand()
1344   hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP  | \  in HAL_DSI_ConfigCommand()
1358   hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;  in HAL_DSI_ConfigCommand()
1359   hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;  in HAL_DSI_ConfigCommand()
1384   hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;  in HAL_DSI_ConfigFlowControl()
1385   hdsi->Instance->PCR |= FlowControl;  in HAL_DSI_ConfigFlowControl()
1422   hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);  in HAL_DSI_ConfigPhyTimer()
1423   hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));  in HAL_DSI_ConfigPhyTimer()
1426   hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);  in HAL_DSI_ConfigPhyTimer()
1427 …hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U)…  in HAL_DSI_ConfigPhyTimer()
1431   hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;  in HAL_DSI_ConfigPhyTimer()
1432   hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);  in HAL_DSI_ConfigPhyTimer()
1454   hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;  in HAL_DSI_ConfigHostTimeouts()
1455   hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);  in HAL_DSI_ConfigHostTimeouts()
1458   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1459   hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);  in HAL_DSI_ConfigHostTimeouts()
1462   hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1463   hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;  in HAL_DSI_ConfigHostTimeouts()
1466   hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1467   hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;  in HAL_DSI_ConfigHostTimeouts()
1470   hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1471   hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;  in HAL_DSI_ConfigHostTimeouts()
1474   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1475   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;  in HAL_DSI_ConfigHostTimeouts()
1478   hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;  in HAL_DSI_ConfigHostTimeouts()
1479   hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;  in HAL_DSI_ConfigHostTimeouts()
1482   hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1483   hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;  in HAL_DSI_ConfigHostTimeouts()
1486   hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;  in HAL_DSI_ConfigHostTimeouts()
1487   hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;  in HAL_DSI_ConfigHostTimeouts()
1553   hdsi->Instance->WCR |= DSI_WCR_LTDCEN;  in HAL_DSI_Refresh()
1578   hdsi->Instance->WCR &= ~DSI_WCR_COLM;  in HAL_DSI_ColorMode()
1579   hdsi->Instance->WCR |= ColorMode;  in HAL_DSI_ColorMode()
1604   hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;  in HAL_DSI_Shutdown()
1605   hdsi->Instance->WCR |= Shutdown;  in HAL_DSI_Shutdown()
1685   while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)  in HAL_DSI_LongWrite()
1705   hdsi->Instance->GPDR = fifoword;  in HAL_DSI_LongWrite()
1718     hdsi->Instance->GPDR = fifoword;  in HAL_DSI_LongWrite()
1725   DSI_ConfigPacketHeader(hdsi->Instance,  in HAL_DSI_LongWrite()
1787     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);  in HAL_DSI_Read()
1791     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);  in HAL_DSI_Read()
1795     DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);  in HAL_DSI_Read()
1799 …DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);  in HAL_DSI_Read()
1815     if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)  in HAL_DSI_Read()
1817       fifoword = hdsi->Instance->GPDR;  in HAL_DSI_Read()
1841     if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)  in HAL_DSI_Read()
1843       if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)  in HAL_DSI_Read()
1876   if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))  in HAL_DSI_EnterULPMData()
1884   if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)  in HAL_DSI_EnterULPMData()
1890   else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)  in HAL_DSI_EnterULPMData()
1902   if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U)  in HAL_DSI_EnterULPMData()
1910   if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)  in HAL_DSI_EnterULPMData()
1937   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_EnterULPMData()
1939     if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)  in HAL_DSI_EnterULPMData()
1946   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_EnterULPMData()
1948     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))  in HAL_DSI_EnterULPMData()
1963   hdsi->Instance->PUCR |= DSI_PUCR_URDL;  in HAL_DSI_EnterULPMData()
1969   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_EnterULPMData()
1971     while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)  in HAL_DSI_EnterULPMData()
1983   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_EnterULPMData()
1985     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)  in HAL_DSI_EnterULPMData()
2026   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPMData()
2028     if ((hdsi->Instance->PSR &  DSI_PSR_UAN0) != 0U)  in HAL_DSI_ExitULPMData()
2036   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPMData()
2038     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0  | DSI_PSR_UAN1)) != 0U)  in HAL_DSI_ExitULPMData()
2078   hdsi->Instance->PUCR |= DSI_PUCR_UEDL;  in HAL_DSI_ExitULPMData()
2084   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPMData()
2086     while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)  in HAL_DSI_ExitULPMData()
2098   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPMData()
2100     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))  in HAL_DSI_ExitULPMData()
2124   hdsi->Instance->PUCR = 0U;  in HAL_DSI_ExitULPMData()
2127   if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)  in HAL_DSI_ExitULPMData()
2135   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPMData()
2137     if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)  in HAL_DSI_ExitULPMData()
2144   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPMData()
2146     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0  |  DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))  in HAL_DSI_ExitULPMData()
2204   if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))  in HAL_DSI_EnterULPM()
2212   if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)  in HAL_DSI_EnterULPM()
2218   else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)  in HAL_DSI_EnterULPM()
2230 …if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U)  in HAL_DSI_EnterULPM()
2238   if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)  in HAL_DSI_EnterULPM()
2265   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_EnterULPM()
2267     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))  in HAL_DSI_EnterULPM()
2274   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_EnterULPM()
2276     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \  in HAL_DSI_EnterULPM()
2292   hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;  in HAL_DSI_EnterULPM()
2298   hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);  in HAL_DSI_EnterULPM()
2304   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_EnterULPM()
2306     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)  in HAL_DSI_EnterULPM()
2318   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_EnterULPM()
2320     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)  in HAL_DSI_EnterULPM()
2364   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPM()
2366     if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \  in HAL_DSI_ExitULPM()
2375   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPM()
2377     if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \  in HAL_DSI_ExitULPM()
2418   hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);  in HAL_DSI_ExitULPM()
2424   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPM()
2426     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))  in HAL_DSI_ExitULPM()
2438   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPM()
2440 …while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI…  in HAL_DSI_ExitULPM()
2465   hdsi->Instance->PUCR = 0U;  in HAL_DSI_ExitULPM()
2471   hdsi->Instance->CLCR |= DSI_CLCR_DPCC;  in HAL_DSI_ExitULPM()
2474   if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)  in HAL_DSI_ExitULPM()
2482   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)  in HAL_DSI_ExitULPM()
2484     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))  in HAL_DSI_ExitULPM()
2491   else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)  in HAL_DSI_ExitULPM()
2493     if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \  in HAL_DSI_ExitULPM()
2555   hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);  in HAL_DSI_PatternGeneratorStart()
2556   hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));  in HAL_DSI_PatternGeneratorStart()
2559   hdsi->Instance->VMCR |= DSI_VMCR_PGE;  in HAL_DSI_PatternGeneratorStart()
2579   hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;  in HAL_DSI_PatternGeneratorStop()
2614         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2615         hdsi->Instance->WPCR[1U] |= Value << 16U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2620         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2621         hdsi->Instance->WPCR[1U] |= Value << 18U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2635         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2636         hdsi->Instance->WPCR[1U] |= Value << 6U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2641         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2642         hdsi->Instance->WPCR[1U] |= Value << 8U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2656         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2657         hdsi->Instance->WPCR[1U] |= Value;  in HAL_DSI_SetSlewRateAndDelayTuning()
2662         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2663         hdsi->Instance->WPCR[1U] |= Value << 2U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2696   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;  in HAL_DSI_SetLowPowerRXFilter()
2697   hdsi->Instance->WPCR[1U] |= Frequency << 25U;  in HAL_DSI_SetLowPowerRXFilter()
2722   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;  in HAL_DSI_SetSDD()
2723   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);  in HAL_DSI_SetSDD()
2759         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;  in HAL_DSI_SetLanePinsConfiguration()
2760         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);  in HAL_DSI_SetLanePinsConfiguration()
2765         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;  in HAL_DSI_SetLanePinsConfiguration()
2766         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);  in HAL_DSI_SetLanePinsConfiguration()
2771         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;  in HAL_DSI_SetLanePinsConfiguration()
2772         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);  in HAL_DSI_SetLanePinsConfiguration()
2786         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;  in HAL_DSI_SetLanePinsConfiguration()
2787         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);  in HAL_DSI_SetLanePinsConfiguration()
2792         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;  in HAL_DSI_SetLanePinsConfiguration()
2793         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);  in HAL_DSI_SetLanePinsConfiguration()
2798         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;  in HAL_DSI_SetLanePinsConfiguration()
2799         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);  in HAL_DSI_SetLanePinsConfiguration()
2842       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;  in HAL_DSI_SetPHYTimings()
2843       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);  in HAL_DSI_SetPHYTimings()
2848         hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;  in HAL_DSI_SetPHYTimings()
2849         hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;  in HAL_DSI_SetPHYTimings()
2855       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;  in HAL_DSI_SetPHYTimings()
2856       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);  in HAL_DSI_SetPHYTimings()
2861         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;  in HAL_DSI_SetPHYTimings()
2862         hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;  in HAL_DSI_SetPHYTimings()
2868       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;  in HAL_DSI_SetPHYTimings()
2869       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);  in HAL_DSI_SetPHYTimings()
2874         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;  in HAL_DSI_SetPHYTimings()
2875         hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;  in HAL_DSI_SetPHYTimings()
2881       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;  in HAL_DSI_SetPHYTimings()
2882       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);  in HAL_DSI_SetPHYTimings()
2887         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;  in HAL_DSI_SetPHYTimings()
2888         hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;  in HAL_DSI_SetPHYTimings()
2894       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;  in HAL_DSI_SetPHYTimings()
2895       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);  in HAL_DSI_SetPHYTimings()
2900         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;  in HAL_DSI_SetPHYTimings()
2901         hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;  in HAL_DSI_SetPHYTimings()
2907       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;  in HAL_DSI_SetPHYTimings()
2908       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);  in HAL_DSI_SetPHYTimings()
2913         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;  in HAL_DSI_SetPHYTimings()
2914         hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;  in HAL_DSI_SetPHYTimings()
2920       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;  in HAL_DSI_SetPHYTimings()
2921       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);  in HAL_DSI_SetPHYTimings()
2926         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;  in HAL_DSI_SetPHYTimings()
2927         hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;  in HAL_DSI_SetPHYTimings()
2933       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;  in HAL_DSI_SetPHYTimings()
2934       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);  in HAL_DSI_SetPHYTimings()
2939         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;  in HAL_DSI_SetPHYTimings()
2940         hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;  in HAL_DSI_SetPHYTimings()
2946       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;  in HAL_DSI_SetPHYTimings()
2947       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);  in HAL_DSI_SetPHYTimings()
2952         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;  in HAL_DSI_SetPHYTimings()
2953         hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;  in HAL_DSI_SetPHYTimings()
2988     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;  in HAL_DSI_ForceTXStopMode()
2989     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);  in HAL_DSI_ForceTXStopMode()
2994     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;  in HAL_DSI_ForceTXStopMode()
2995     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);  in HAL_DSI_ForceTXStopMode()
3027   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;  in HAL_DSI_ForceRXLowPower()
3028   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);  in HAL_DSI_ForceRXLowPower()
3052   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;  in HAL_DSI_ForceDataLanesInRX()
3053   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);  in HAL_DSI_ForceDataLanesInRX()
3077   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;  in HAL_DSI_SetPullDown()
3078   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);  in HAL_DSI_SetPullDown()
3102   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;  in HAL_DSI_SetContentionDetectionOff()
3103   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);  in HAL_DSI_SetContentionDetectionOff()