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Searched refs:IWDG_SR_ONF (Results 1 – 25 of 37) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_iwdg.h406 return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); in LL_IWDG_IsActiveFlag_ONF()
Dstm32h5xx_hal_iwdg.h143 #define IWDG_STATUS_ENABLE IWDG_SR_ONF
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_iwdg.h406 return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); in LL_IWDG_IsActiveFlag_ONF()
Dstm32u0xx_hal_iwdg.h143 #define IWDG_STATUS_ENABLE IWDG_SR_ONF
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_iwdg.h406 return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); in LL_IWDG_IsActiveFlag_ONF()
Dstm32h7rsxx_hal_iwdg.h143 #define IWDG_STATUS_ENABLE IWDG_SR_ONF
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_iwdg.h406 return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); in LL_IWDG_IsActiveFlag_ONF()
Dstm32wbaxx_hal_iwdg.h143 #define IWDG_STATUS_ENABLE IWDG_SR_ONF
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_iwdg.h406 return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); in LL_IWDG_IsActiveFlag_ONF()
Dstm32n6xx_hal_iwdg.h143 #define IWDG_STATUS_ENABLE IWDG_SR_ONF
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_iwdg.c437 status = (hiwdg->Instance->SR & IWDG_SR_ONF); in HAL_IWDG_GetActiveStatus()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_iwdg.c438 status = (hiwdg->Instance->SR & IWDG_SR_ONF); in HAL_IWDG_GetActiveStatus()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_iwdg.c438 status = (hiwdg->Instance->SR & IWDG_SR_ONF); in HAL_IWDG_GetActiveStatus()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_iwdg.c438 status = (hiwdg->Instance->SR & IWDG_SR_ONF); in HAL_IWDG_GetActiveStatus()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_iwdg.c438 status = (hiwdg->Instance->SR & IWDG_SR_ONF); in HAL_IWDG_GetActiveStatus()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h4619 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog e… macro
Dstm32wba52xx.h8220 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog e… macro
Dstm32wba54xx.h8454 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog e… macro
Dstm32wba5mxx.h8454 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog e… macro
Dstm32wba55xx.h8454 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog e… macro
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h4256 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog Enable… macro
Dstm32u083xx.h4795 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog Enable… macro
Dstm32u073xx.h4537 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog Enable… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h12436 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog E… macro
Dstm32h523xx.h18422 #define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog E… macro

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