/hal_stm32-latest/stm32cube/stm32f0xx/soc/ |
D | stm32f030x6.h | 2502 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2503 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f030x8.h | 2532 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2533 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f070x6.h | 2555 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2556 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f031x6.h | 2601 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2602 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f030xc.h | 2783 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2784 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f038xx.h | 2600 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2601 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f070xb.h | 2635 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2636 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f058xx.h | 3049 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3050 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32f051x8.h | 3050 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3051 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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/hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
D | stm32l041xx.h | 2842 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2843 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l010x8.h | 2575 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2576 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l010xb.h | 2583 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2584 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l011xx.h | 2648 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2649 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l021xx.h | 2776 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2777 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l031xx.h | 2714 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2715 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l051xx.h | 2755 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2756 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l010x4.h | 2567 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2568 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l010x6.h | 2573 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2574 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l081xx.h | 2929 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2930 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l071xx.h | 2801 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 2802 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l052xx.h | 3044 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3045 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l062xx.h | 3172 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3173 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32l053xx.h | 3066 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3067 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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/hal_stm32-latest/stm32cube/stm32c0xx/soc/ |
D | stm32c011xx.h | 3335 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3336 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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D | stm32c031xx.h | 3342 #define I2C_OAR2_OA2MASK05_Pos (8U) macro 3343 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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