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Searched refs:I2C_CR1_TXIE (Results 1 – 25 of 274) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_i2c.h154 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1010 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1021 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1032 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
Dstm32wlxx_hal_smbus.h372 #define SMBUS_IT_TXI I2C_CR1_TXIE
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1390 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1412 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
Dstm32l0xx_hal_smbus.h372 #define SMBUS_IT_TXI I2C_CR1_TXIE
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1291 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1302 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1313 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
Dstm32f0xx_hal_smbus.h370 #define SMBUS_IT_TXI I2C_CR1_TXIE
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1291 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1302 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1313 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1249 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1260 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1271 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1249 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1260 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1271 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_i2c.h158 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1382 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1393 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1404 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1390 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1412 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
Dstm32n6xx_hal_smbus.h369 #define SMBUS_IT_TXI I2C_CR1_TXIE
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_i2c.h166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1289 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1300 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1311 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_i2c.h167 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1461 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1472 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1483 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_i2c.h169 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable …
1473 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_EnableIT_TX()
1484 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); in LL_I2C_DisableIT_TX()
1495 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_TX()
Dstm32wbaxx_hal_smbus.h371 #define SMBUS_IT_TXI I2C_CR1_TXIE

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