1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_ll_i2c.h
4   * @author  MCD Application Team
5   * @brief   Header file of I2C LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2022 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_I2C_H
21 #define STM32H7RSxx_LL_I2C_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29 
30 /** @addtogroup STM32H7RSxx_LL_Driver
31   * @{
32   */
33 
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
35 
36 /** @defgroup I2C_LL I2C
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45   * @{
46   */
47 /**
48   * @}
49   */
50 
51 /* Private macros ------------------------------------------------------------*/
52 
53 /* Exported types ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
56   * @{
57   */
58 typedef struct
59 {
60   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
61                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
62 
63                                      This feature can be modified afterwards using unitary function
64                                      @ref LL_I2C_SetMode(). */
65 
66   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
67                                      This parameter must be set by referring to the STM32CubeMX Tool and
68                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
69 
70                                      This feature can be modified afterwards using unitary function
71                                      @ref LL_I2C_SetTiming(). */
72 
73   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
74                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
75 
76                                      This feature can be modified afterwards using unitary functions
77                                      @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
78 
79   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
80                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
81 
82                                      This feature can be modified afterwards using unitary function
83                                      @ref LL_I2C_SetDigitalFilter(). */
84 
85   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
86                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
87 
88                                      This feature can be modified afterwards using unitary function
89                                      @ref LL_I2C_SetOwnAddress1(). */
90 
91   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
92                                      match code or next received byte.
93                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
94 
95                                      This feature can be modified afterwards using unitary function
96                                      @ref LL_I2C_AcknowledgeNextData(). */
97 
98   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
99                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
100 
101                                      This feature can be modified afterwards using unitary function
102                                      @ref LL_I2C_SetOwnAddress1(). */
103 } LL_I2C_InitTypeDef;
104 /**
105   * @}
106   */
107 #endif /*USE_FULL_LL_DRIVER*/
108 
109 /* Exported constants --------------------------------------------------------*/
110 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
111   * @{
112   */
113 
114 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
115   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
116   * @{
117   */
118 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
119 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
120 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
121 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
122 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
123 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
124 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
125 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
126 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
127 /**
128   * @}
129   */
130 
131 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
132   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
133   * @{
134   */
135 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
136 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
137 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
138 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
139 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
140 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
141 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
142 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
143 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
144 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
145 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
146 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
147 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
148 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
149 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
150 /**
151   * @}
152   */
153 
154 /** @defgroup I2C_LL_EC_IT IT Defines
155   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
156   * @{
157   */
158 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
159 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
160 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
161 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
162 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
163 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
164 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
165 /**
166   * @}
167   */
168 
169 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
170   * @{
171   */
172 #define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
173 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
174 #define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
175                                                                          (Default address not acknowledge)        */
176 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
177 /**
178   * @}
179   */
180 
181 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
182   * @{
183   */
184 #define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */
185 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
186 /**
187   * @}
188   */
189 
190 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
191   * @{
192   */
193 #define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */
194 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
195 /**
196   * @}
197   */
198 
199 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
200   * @{
201   */
202 #define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */
203 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
204 /**
205   * @}
206   */
207 
208 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
209   * @{
210   */
211 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
212 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
213 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
214 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
215 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
216 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
217 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
218 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
219                                                                          All Address2 are acknowledged.        */
220 /**
221   * @}
222   */
223 
224 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
225   * @{
226   */
227 #define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */
228 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
229 /**
230   * @}
231   */
232 
233 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
234   * @{
235   */
236 #define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */
237 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
238 /**
239   * @}
240   */
241 
242 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
243   * @{
244   */
245 #define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */
246 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
247 /**
248   * @}
249   */
250 
251 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
252   * @{
253   */
254 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
255 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
256                                                                           with no HW PEC comparison.  */
257 #define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
258                                                                           with no HW PEC comparison.  */
259 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
260                                                                           with HW PEC comparison.     */
261 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
262                                                                           with HW PEC comparison.     */
263 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
264                                                                           with HW PEC comparison.     */
265 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
266 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
267 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
268 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
269 /**
270   * @}
271   */
272 
273 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
274   * @{
275   */
276 #define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
277 /*!< Don't Generate Stop and Start condition. */
278 #define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
279 /*!< Generate Stop condition (Size should be set to 0).      */
280 #define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
281 /*!< Generate Start for read request. */
282 #define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
283 /*!< Generate Start for write request. */
284 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
285 /*!< Generate Restart for read request, slave 7Bit address.  */
286 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
287 /*!< Generate Restart for write request, slave 7Bit address. */
288 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
289                                                        I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
290 /*!< Generate Restart for read request, slave 10Bit address. */
291 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
292 /*!< Generate Restart for write request, slave 10Bit address.*/
293 /**
294   * @}
295   */
296 
297 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
298   * @{
299   */
300 #define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
301                                                                           slave enters receiver mode.  */
302 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
303                                                                           slave enters transmitter mode.*/
304 /**
305   * @}
306   */
307 
308 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
309   * @{
310   */
311 #define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
312                                                                           transmission */
313 #define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
314                                                                           reception */
315 /**
316   * @}
317   */
318 
319 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
320   * @{
321   */
322 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
323                                                                           SCL low level timeout.              */
324 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
325                                                                           both SCL and SDA high level timeout.*/
326 /**
327   * @}
328   */
329 
330 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
331   * @{
332   */
333 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
334 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
335                                                                                        enable bit                   */
336 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
337                                                        I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
338 (extended clock) enable bits */
339 /**
340   * @}
341   */
342 
343 /**
344   * @}
345   */
346 
347 /* Exported macro ------------------------------------------------------------*/
348 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
349   * @{
350   */
351 
352 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
353   * @{
354   */
355 
356 /**
357   * @brief  Write a value in I2C register
358   * @param  __INSTANCE__ I2C Instance
359   * @param  __REG__ Register to be written
360   * @param  __VALUE__ Value to be written in the register
361   * @retval None
362   */
363 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
364 
365 /**
366   * @brief  Read a value in I2C register
367   * @param  __INSTANCE__ I2C Instance
368   * @param  __REG__ Register to be read
369   * @retval Register value
370   */
371 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
372 /**
373   * @}
374   */
375 
376 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
377   * @{
378   */
379 /**
380   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
381   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
382   * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
383                            (tscldel = (SCLDEL+1)xtpresc)
384   * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
385                            (tsdadel = SDADELxtpresc)
386   * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
387                             (tsclh = (SCLH+1)xtpresc)
388   * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
389                             (tscll = (SCLL+1)xtpresc)
390   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
391   */
392 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
393   ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
394    (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
395    (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
396    (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
397    (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
398 /**
399   * @}
400   */
401 
402 /**
403   * @}
404   */
405 
406 /* Exported functions --------------------------------------------------------*/
407 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
408   * @{
409   */
410 
411 /** @defgroup I2C_LL_EF_Configuration Configuration
412   * @{
413   */
414 
415 /**
416   * @brief  Enable I2C peripheral (PE = 1).
417   * @rmtoll CR1          PE            LL_I2C_Enable
418   * @param  I2Cx I2C Instance.
419   * @retval None
420   */
LL_I2C_Enable(I2C_TypeDef * I2Cx)421 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
422 {
423   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
424 }
425 
426 /**
427   * @brief  Disable I2C peripheral (PE = 0).
428   * @note   When PE = 0, the I2C SCL and SDA lines are released.
429   *         Internal state machines and status bits are put back to their reset value.
430   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
431   * @rmtoll CR1          PE            LL_I2C_Disable
432   * @param  I2Cx I2C Instance.
433   * @retval None
434   */
LL_I2C_Disable(I2C_TypeDef * I2Cx)435 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
436 {
437   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
438 }
439 
440 /**
441   * @brief  Check if the I2C peripheral is enabled or disabled.
442   * @rmtoll CR1          PE            LL_I2C_IsEnabled
443   * @param  I2Cx I2C Instance.
444   * @retval State of bit (1 or 0).
445   */
LL_I2C_IsEnabled(const I2C_TypeDef * I2Cx)446 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
447 {
448   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
449 }
450 
451 /**
452   * @brief  Configure Noise Filters (Analog and Digital).
453   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
454   *         The filters can only be programmed when the I2C is disabled (PE = 0).
455   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
456   *         CR1          DNF           LL_I2C_ConfigFilters
457   * @param  I2Cx I2C Instance.
458   * @param  AnalogFilter This parameter can be one of the following values:
459   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
460   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
461   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
462                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
463   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
464   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
465   * @retval None
466   */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)467 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
468 {
469   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
470 }
471 
472 /**
473   * @brief  Configure Digital Noise Filter.
474   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
475   *         This filter can only be programmed when the I2C is disabled (PE = 0).
476   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
477   * @param  I2Cx I2C Instance.
478   * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
479                           and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
480   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
481   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
482   * @retval None
483   */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)484 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
485 {
486   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
487 }
488 
489 /**
490   * @brief  Get the current Digital Noise Filter configuration.
491   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
492   * @param  I2Cx I2C Instance.
493   * @retval Value between Min_Data=0x0 and Max_Data=0xF
494   */
LL_I2C_GetDigitalFilter(const I2C_TypeDef * I2Cx)495 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
496 {
497   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
498 }
499 
500 /**
501   * @brief  Enable Analog Noise Filter.
502   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
503   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
504   * @param  I2Cx I2C Instance.
505   * @retval None
506   */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)507 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
508 {
509   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
510 }
511 
512 /**
513   * @brief  Disable Analog Noise Filter.
514   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
515   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
516   * @param  I2Cx I2C Instance.
517   * @retval None
518   */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)519 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
520 {
521   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
522 }
523 
524 /**
525   * @brief  Check if Analog Noise Filter is enabled or disabled.
526   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
527   * @param  I2Cx I2C Instance.
528   * @retval State of bit (1 or 0).
529   */
LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef * I2Cx)530 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
531 {
532   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
533 }
534 
535 /**
536   * @brief  Enable DMA transmission requests.
537   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
538   * @param  I2Cx I2C Instance.
539   * @retval None
540   */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)541 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
542 {
543   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
544 }
545 
546 /**
547   * @brief  Disable DMA transmission requests.
548   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
549   * @param  I2Cx I2C Instance.
550   * @retval None
551   */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)552 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
553 {
554   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
555 }
556 
557 /**
558   * @brief  Check if DMA transmission requests are enabled or disabled.
559   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
560   * @param  I2Cx I2C Instance.
561   * @retval State of bit (1 or 0).
562   */
LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef * I2Cx)563 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
564 {
565   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
566 }
567 
568 /**
569   * @brief  Enable DMA reception requests.
570   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
571   * @param  I2Cx I2C Instance.
572   * @retval None
573   */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)574 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
575 {
576   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
577 }
578 
579 /**
580   * @brief  Disable DMA reception requests.
581   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
582   * @param  I2Cx I2C Instance.
583   * @retval None
584   */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)585 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
586 {
587   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
588 }
589 
590 /**
591   * @brief  Check if DMA reception requests are enabled or disabled.
592   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
593   * @param  I2Cx I2C Instance.
594   * @retval State of bit (1 or 0).
595   */
LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef * I2Cx)596 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
597 {
598   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
599 }
600 
601 /**
602   * @brief  Get the data register address used for DMA transfer
603   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
604   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
605   * @param  I2Cx I2C Instance
606   * @param  Direction This parameter can be one of the following values:
607   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
608   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
609   * @retval Address of data register
610   */
LL_I2C_DMA_GetRegAddr(const I2C_TypeDef * I2Cx,uint32_t Direction)611 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
612 {
613   uint32_t data_reg_addr;
614 
615   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
616   {
617     /* return address of TXDR register */
618     data_reg_addr = (uint32_t) &(I2Cx->TXDR);
619   }
620   else
621   {
622     /* return address of RXDR register */
623     data_reg_addr = (uint32_t) &(I2Cx->RXDR);
624   }
625 
626   return data_reg_addr;
627 }
628 
629 /**
630   * @brief  Enable Clock stretching.
631   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
632   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
633   * @param  I2Cx I2C Instance.
634   * @retval None
635   */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)636 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
637 {
638   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
639 }
640 
641 /**
642   * @brief  Disable Clock stretching.
643   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
644   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
645   * @param  I2Cx I2C Instance.
646   * @retval None
647   */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)648 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
649 {
650   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
651 }
652 
653 /**
654   * @brief  Check if Clock stretching is enabled or disabled.
655   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
656   * @param  I2Cx I2C Instance.
657   * @retval State of bit (1 or 0).
658   */
LL_I2C_IsEnabledClockStretching(const I2C_TypeDef * I2Cx)659 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
660 {
661   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
662 }
663 
664 /**
665   * @brief  Enable hardware byte control in slave mode.
666   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
667   * @param  I2Cx I2C Instance.
668   * @retval None
669   */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)670 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
671 {
672   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
673 }
674 
675 /**
676   * @brief  Disable hardware byte control in slave mode.
677   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
678   * @param  I2Cx I2C Instance.
679   * @retval None
680   */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)681 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
682 {
683   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
684 }
685 
686 /**
687   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
688   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
689   * @param  I2Cx I2C Instance.
690   * @retval State of bit (1 or 0).
691   */
LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef * I2Cx)692 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
693 {
694   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
695 }
696 
697 /**
698   * @brief  Enable Wakeup from STOP.
699   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
700   *         WakeUpFromStop feature is supported by the I2Cx Instance.
701   * @note   This bit can only be programmed when Digital Filter is disabled.
702   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
703   * @param  I2Cx I2C Instance.
704   * @retval None
705   */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)706 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
707 {
708   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
709 }
710 
711 /**
712   * @brief  Disable Wakeup from STOP.
713   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
714   *         WakeUpFromStop feature is supported by the I2Cx Instance.
715   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
716   * @param  I2Cx I2C Instance.
717   * @retval None
718   */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)719 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
720 {
721   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
722 }
723 
724 /**
725   * @brief  Check if Wakeup from STOP is enabled or disabled.
726   * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
727   *         WakeUpFromStop feature is supported by the I2Cx Instance.
728   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
729   * @param  I2Cx I2C Instance.
730   * @retval State of bit (1 or 0).
731   */
LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef * I2Cx)732 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
733 {
734   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
735 }
736 
737 /**
738   * @brief  Enable General Call.
739   * @note   When enabled the Address 0x00 is ACKed.
740   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
741   * @param  I2Cx I2C Instance.
742   * @retval None
743   */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)744 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
745 {
746   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
747 }
748 
749 /**
750   * @brief  Disable General Call.
751   * @note   When disabled the Address 0x00 is NACKed.
752   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
753   * @param  I2Cx I2C Instance.
754   * @retval None
755   */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)756 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
757 {
758   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
759 }
760 
761 /**
762   * @brief  Check if General Call is enabled or disabled.
763   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
764   * @param  I2Cx I2C Instance.
765   * @retval State of bit (1 or 0).
766   */
LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef * I2Cx)767 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
768 {
769   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
770 }
771 
772 /**
773   * @brief  Enable I2C Fast Mode Plus (FMP = 1).
774   * @note   20mA I/O drive enable
775   * @rmtoll CR1          FMP           LL_I2C_EnableFastModePlus
776   * @param  I2Cx I2C Instance.
777   * @retval None
778   */
LL_I2C_EnableFastModePlus(I2C_TypeDef * I2Cx)779 __STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
780 {
781   SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
782 }
783 
784 /**
785   * @brief  Disable I2C Fast Mode Plus (FMP = 0).
786   * @note   20mA I/O drive disable
787   * @rmtoll CR1          FMP           LL_I2C_DisableFastModePlus
788   * @param  I2Cx I2C Instance.
789   * @retval None
790   */
LL_I2C_DisableFastModePlus(I2C_TypeDef * I2Cx)791 __STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
792 {
793   CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
794 }
795 
796 /**
797   * @brief  Check if the I2C Fast Mode Plus is enabled or disabled.
798   * @rmtoll CR1          FMP           LL_I2C_IsEnabledFastModePlus
799   * @param  I2Cx I2C Instance.
800   * @retval State of bit (1 or 0).
801   */
LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef * I2Cx)802 __STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx)
803 {
804   return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
805 }
806 
807 /**
808   * @brief  Enable automatic clear of ADDR flag.
809   * @rmtoll CR1          ADDRACLR      LL_I2C_EnableAutoClearFlag_ADDR
810   * @param  I2Cx I2C Instance.
811   * @retval None
812   */
LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)813 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
814 {
815   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
816 }
817 
818 /**
819   * @brief  Disable automatic clear of ADDR flag.
820   * @rmtoll CR1          ADDRACLR      LL_I2C_DisableAutoClearFlag_ADDR
821   * @param  I2Cx I2C Instance.
822   * @retval None
823   */
LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)824 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
825 {
826   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
827 }
828 
829 /**
830   * @brief  Check if the automatic clear of ADDR flag is enabled or disabled.
831   * @rmtoll CR1          ADDRACLR      LL_I2C_IsEnabledAutoClearFlag_ADDR
832   * @param  I2Cx I2C Instance.
833   * @retval State of bit (1 or 0).
834   */
LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef * I2Cx)835 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx)
836 {
837   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
838 }
839 
840 /**
841   * @brief  Enable automatic clear of STOP flag.
842   * @rmtoll CR1          STOPFACLR     LL_I2C_EnableAutoClearFlag_STOP
843   * @param  I2Cx I2C Instance.
844   * @retval None
845   */
LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)846 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
847 {
848   SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
849 }
850 
851 /**
852   * @brief  Disable automatic clear of STOP flag.
853   * @rmtoll CR1          STOPFACLR     LL_I2C_DisableAutoClearFlag_STOP
854   * @param  I2Cx I2C Instance.
855   * @retval None
856   */
LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)857 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
858 {
859   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
860 }
861 
862 /**
863   * @brief  Check if the automatic clear of STOP flag is enabled or disabled.
864   * @rmtoll CR1          STOPFACLR     LL_I2C_IsEnabledAutoClearFlag_STOP
865   * @param  I2Cx I2C Instance.
866   * @retval State of bit (1 or 0).
867   */
LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef * I2Cx)868 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx)
869 {
870   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
871 }
872 
873 /**
874   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
875   * @note   Changing this bit is not allowed, when the START bit is set.
876   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
877   * @param  I2Cx I2C Instance.
878   * @param  AddressingMode This parameter can be one of the following values:
879   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
880   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
881   * @retval None
882   */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)883 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
884 {
885   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
886 }
887 
888 /**
889   * @brief  Get the Master addressing mode.
890   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
891   * @param  I2Cx I2C Instance.
892   * @retval Returned value can be one of the following values:
893   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
894   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
895   */
LL_I2C_GetMasterAddressingMode(const I2C_TypeDef * I2Cx)896 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
897 {
898   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
899 }
900 
901 /**
902   * @brief  Set the Own Address1.
903   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
904   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
905   * @param  I2Cx I2C Instance.
906   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
907   * @param  OwnAddrSize This parameter can be one of the following values:
908   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
909   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
910   * @retval None
911   */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)912 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
913 {
914   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
915 }
916 
917 /**
918   * @brief  Enable acknowledge on Own Address1 match address.
919   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
920   * @param  I2Cx I2C Instance.
921   * @retval None
922   */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)923 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
924 {
925   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
926 }
927 
928 /**
929   * @brief  Disable acknowledge on Own Address1 match address.
930   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
931   * @param  I2Cx I2C Instance.
932   * @retval None
933   */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)934 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
935 {
936   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
937 }
938 
939 /**
940   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
941   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
942   * @param  I2Cx I2C Instance.
943   * @retval State of bit (1 or 0).
944   */
LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef * I2Cx)945 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
946 {
947   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
948 }
949 
950 /**
951   * @brief  Set the 7bits Own Address2.
952   * @note   This action has no effect if own address2 is enabled.
953   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
954   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
955   * @param  I2Cx I2C Instance.
956   * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
957   * @param  OwnAddrMask This parameter can be one of the following values:
958   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
959   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
960   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
961   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
962   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
963   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
964   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
965   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
966   * @retval None
967   */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)968 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
969 {
970   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
971 }
972 
973 /**
974   * @brief  Enable acknowledge on Own Address2 match address.
975   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
976   * @param  I2Cx I2C Instance.
977   * @retval None
978   */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)979 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
980 {
981   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
982 }
983 
984 /**
985   * @brief  Disable  acknowledge on Own Address2 match address.
986   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
987   * @param  I2Cx I2C Instance.
988   * @retval None
989   */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)990 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
991 {
992   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
993 }
994 
995 /**
996   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
997   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
998   * @param  I2Cx I2C Instance.
999   * @retval State of bit (1 or 0).
1000   */
LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef * I2Cx)1001 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
1002 {
1003   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
1004 }
1005 
1006 /**
1007   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
1008   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
1009   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
1010   * @param  I2Cx I2C Instance.
1011   * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1012   * @note   This parameter is computed with the STM32CubeMX Tool.
1013   * @retval None
1014   */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)1015 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
1016 {
1017   WRITE_REG(I2Cx->TIMINGR, Timing);
1018 }
1019 
1020 /**
1021   * @brief  Get the Timing Prescaler setting.
1022   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
1023   * @param  I2Cx I2C Instance.
1024   * @retval Value between Min_Data=0x0 and Max_Data=0xF
1025   */
LL_I2C_GetTimingPrescaler(const I2C_TypeDef * I2Cx)1026 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
1027 {
1028   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
1029 }
1030 
1031 /**
1032   * @brief  Get the SCL low period setting.
1033   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
1034   * @param  I2Cx I2C Instance.
1035   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1036   */
LL_I2C_GetClockLowPeriod(const I2C_TypeDef * I2Cx)1037 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
1038 {
1039   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
1040 }
1041 
1042 /**
1043   * @brief  Get the SCL high period setting.
1044   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
1045   * @param  I2Cx I2C Instance.
1046   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1047   */
LL_I2C_GetClockHighPeriod(const I2C_TypeDef * I2Cx)1048 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
1049 {
1050   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
1051 }
1052 
1053 /**
1054   * @brief  Get the SDA hold time.
1055   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
1056   * @param  I2Cx I2C Instance.
1057   * @retval Value between Min_Data=0x0 and Max_Data=0xF
1058   */
LL_I2C_GetDataHoldTime(const I2C_TypeDef * I2Cx)1059 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
1060 {
1061   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
1062 }
1063 
1064 /**
1065   * @brief  Get the SDA setup time.
1066   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
1067   * @param  I2Cx I2C Instance.
1068   * @retval Value between Min_Data=0x0 and Max_Data=0xF
1069   */
LL_I2C_GetDataSetupTime(const I2C_TypeDef * I2Cx)1070 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
1071 {
1072   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
1073 }
1074 
1075 /**
1076   * @brief  Configure peripheral mode.
1077   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1078   *         SMBus feature is supported by the I2Cx Instance.
1079   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
1080   *         CR1          SMBDEN        LL_I2C_SetMode
1081   * @param  I2Cx I2C Instance.
1082   * @param  PeripheralMode This parameter can be one of the following values:
1083   *         @arg @ref LL_I2C_MODE_I2C
1084   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
1085   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1086   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1087   * @retval None
1088   */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)1089 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
1090 {
1091   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1092 }
1093 
1094 /**
1095   * @brief  Get peripheral mode.
1096   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1097   *         SMBus feature is supported by the I2Cx Instance.
1098   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
1099   *         CR1          SMBDEN        LL_I2C_GetMode
1100   * @param  I2Cx I2C Instance.
1101   * @retval Returned value can be one of the following values:
1102   *         @arg @ref LL_I2C_MODE_I2C
1103   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
1104   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1105   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1106   */
LL_I2C_GetMode(const I2C_TypeDef * I2Cx)1107 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
1108 {
1109   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1110 }
1111 
1112 /**
1113   * @brief  Enable SMBus alert (Host or Device mode)
1114   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1115   *         SMBus feature is supported by the I2Cx Instance.
1116   * @note   SMBus Device mode:
1117   *         - SMBus Alert pin is drived low and
1118   *           Alert Response Address Header acknowledge is enabled.
1119   *         SMBus Host mode:
1120   *         - SMBus Alert pin management is supported.
1121   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
1122   * @param  I2Cx I2C Instance.
1123   * @retval None
1124   */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1125 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1126 {
1127   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1128 }
1129 
1130 /**
1131   * @brief  Disable SMBus alert (Host or Device mode)
1132   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1133   *         SMBus feature is supported by the I2Cx Instance.
1134   * @note   SMBus Device mode:
1135   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1136   *           Alert Response Address Header acknowledge is disabled.
1137   *         SMBus Host mode:
1138   *         - SMBus Alert pin management is not supported.
1139   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
1140   * @param  I2Cx I2C Instance.
1141   * @retval None
1142   */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1143 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1144 {
1145   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1146 }
1147 
1148 /**
1149   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
1150   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1151   *         SMBus feature is supported by the I2Cx Instance.
1152   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
1153   * @param  I2Cx I2C Instance.
1154   * @retval State of bit (1 or 0).
1155   */
LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef * I2Cx)1156 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
1157 {
1158   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1159 }
1160 
1161 /**
1162   * @brief  Enable SMBus Packet Error Calculation (PEC).
1163   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1164   *         SMBus feature is supported by the I2Cx Instance.
1165   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
1166   * @param  I2Cx I2C Instance.
1167   * @retval None
1168   */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1169 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1170 {
1171   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1172 }
1173 
1174 /**
1175   * @brief  Disable SMBus Packet Error Calculation (PEC).
1176   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1177   *         SMBus feature is supported by the I2Cx Instance.
1178   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
1179   * @param  I2Cx I2C Instance.
1180   * @retval None
1181   */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1182 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1183 {
1184   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1185 }
1186 
1187 /**
1188   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1189   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1190   *         SMBus feature is supported by the I2Cx Instance.
1191   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
1192   * @param  I2Cx I2C Instance.
1193   * @retval State of bit (1 or 0).
1194   */
LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef * I2Cx)1195 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
1196 {
1197   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1198 }
1199 
1200 /**
1201   * @brief  Configure the SMBus Clock Timeout.
1202   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1203   *         SMBus feature is supported by the I2Cx Instance.
1204   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1205   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
1206   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
1207   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
1208   * @param  I2Cx I2C Instance.
1209   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1210   * @param  TimeoutAMode This parameter can be one of the following values:
1211   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1212   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1213   * @param  TimeoutB
1214   * @retval None
1215   */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1216 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1217                                                uint32_t TimeoutB)
1218 {
1219   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1220              TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1221 }
1222 
1223 /**
1224   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1225   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1226   *         SMBus feature is supported by the I2Cx Instance.
1227   * @note   These bits can only be programmed when TimeoutA is disabled.
1228   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
1229   * @param  I2Cx I2C Instance.
1230   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1231   * @retval None
1232   */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1233 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1234 {
1235   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1236 }
1237 
1238 /**
1239   * @brief  Get the SMBus Clock TimeoutA setting.
1240   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1241   *         SMBus feature is supported by the I2Cx Instance.
1242   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
1243   * @param  I2Cx I2C Instance.
1244   * @retval Value between Min_Data=0 and Max_Data=0xFFF
1245   */
LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef * I2Cx)1246 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
1247 {
1248   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1249 }
1250 
1251 /**
1252   * @brief  Set the SMBus Clock TimeoutA mode.
1253   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1254   *         SMBus feature is supported by the I2Cx Instance.
1255   * @note   This bit can only be programmed when TimeoutA is disabled.
1256   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
1257   * @param  I2Cx I2C Instance.
1258   * @param  TimeoutAMode This parameter can be one of the following values:
1259   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1260   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1261   * @retval None
1262   */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1263 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1264 {
1265   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1266 }
1267 
1268 /**
1269   * @brief  Get the SMBus Clock TimeoutA mode.
1270   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1271   *         SMBus feature is supported by the I2Cx Instance.
1272   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
1273   * @param  I2Cx I2C Instance.
1274   * @retval Returned value can be one of the following values:
1275   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1276   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1277   */
LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef * I2Cx)1278 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
1279 {
1280   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1281 }
1282 
1283 /**
1284   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1285   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1286   *         SMBus feature is supported by the I2Cx Instance.
1287   * @note   These bits can only be programmed when TimeoutB is disabled.
1288   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
1289   * @param  I2Cx I2C Instance.
1290   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
1291   * @retval None
1292   */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1293 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1294 {
1295   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1296 }
1297 
1298 /**
1299   * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
1300   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1301   *         SMBus feature is supported by the I2Cx Instance.
1302   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
1303   * @param  I2Cx I2C Instance.
1304   * @retval Value between Min_Data=0 and Max_Data=0xFFF
1305   */
LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef * I2Cx)1306 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
1307 {
1308   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1309 }
1310 
1311 /**
1312   * @brief  Enable the SMBus Clock Timeout.
1313   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1314   *         SMBus feature is supported by the I2Cx Instance.
1315   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
1316   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
1317   * @param  I2Cx I2C Instance.
1318   * @param  ClockTimeout This parameter can be one of the following values:
1319   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
1320   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
1321   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1322   * @retval None
1323   */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1324 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1325 {
1326   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1327 }
1328 
1329 /**
1330   * @brief  Disable the SMBus Clock Timeout.
1331   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1332   *         SMBus feature is supported by the I2Cx Instance.
1333   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
1334   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
1335   * @param  I2Cx I2C Instance.
1336   * @param  ClockTimeout This parameter can be one of the following values:
1337   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
1338   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
1339   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1340   * @retval None
1341   */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1342 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1343 {
1344   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1345 }
1346 
1347 /**
1348   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
1349   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1350   *         SMBus feature is supported by the I2Cx Instance.
1351   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
1352   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
1353   * @param  I2Cx I2C Instance.
1354   * @param  ClockTimeout This parameter can be one of the following values:
1355   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
1356   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
1357   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1358   * @retval State of bit (1 or 0).
1359   */
LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1360 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1361 {
1362   return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1363            (ClockTimeout)) ? 1UL : 0UL);
1364 }
1365 
1366 /**
1367   * @}
1368   */
1369 
1370 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1371   * @{
1372   */
1373 
1374 /**
1375   * @brief  Enable TXIS interrupt.
1376   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
1377   * @param  I2Cx I2C Instance.
1378   * @retval None
1379   */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1380 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1381 {
1382   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1383 }
1384 
1385 /**
1386   * @brief  Disable TXIS interrupt.
1387   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
1388   * @param  I2Cx I2C Instance.
1389   * @retval None
1390   */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1391 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1392 {
1393   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1394 }
1395 
1396 /**
1397   * @brief  Check if the TXIS Interrupt is enabled or disabled.
1398   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
1399   * @param  I2Cx I2C Instance.
1400   * @retval State of bit (1 or 0).
1401   */
LL_I2C_IsEnabledIT_TX(const I2C_TypeDef * I2Cx)1402 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1403 {
1404   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1405 }
1406 
1407 /**
1408   * @brief  Enable RXNE interrupt.
1409   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
1410   * @param  I2Cx I2C Instance.
1411   * @retval None
1412   */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1413 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1414 {
1415   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1416 }
1417 
1418 /**
1419   * @brief  Disable RXNE interrupt.
1420   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
1421   * @param  I2Cx I2C Instance.
1422   * @retval None
1423   */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1424 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1425 {
1426   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1427 }
1428 
1429 /**
1430   * @brief  Check if the RXNE Interrupt is enabled or disabled.
1431   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
1432   * @param  I2Cx I2C Instance.
1433   * @retval State of bit (1 or 0).
1434   */
LL_I2C_IsEnabledIT_RX(const I2C_TypeDef * I2Cx)1435 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1436 {
1437   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1438 }
1439 
1440 /**
1441   * @brief  Enable Address match interrupt (slave mode only).
1442   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
1443   * @param  I2Cx I2C Instance.
1444   * @retval None
1445   */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1446 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1447 {
1448   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1449 }
1450 
1451 /**
1452   * @brief  Disable Address match interrupt (slave mode only).
1453   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
1454   * @param  I2Cx I2C Instance.
1455   * @retval None
1456   */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1457 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1458 {
1459   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1460 }
1461 
1462 /**
1463   * @brief  Check if Address match interrupt is enabled or disabled.
1464   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
1465   * @param  I2Cx I2C Instance.
1466   * @retval State of bit (1 or 0).
1467   */
LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef * I2Cx)1468 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1469 {
1470   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1471 }
1472 
1473 /**
1474   * @brief  Enable Not acknowledge received interrupt.
1475   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
1476   * @param  I2Cx I2C Instance.
1477   * @retval None
1478   */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1479 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1480 {
1481   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1482 }
1483 
1484 /**
1485   * @brief  Disable Not acknowledge received interrupt.
1486   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
1487   * @param  I2Cx I2C Instance.
1488   * @retval None
1489   */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1490 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1491 {
1492   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1493 }
1494 
1495 /**
1496   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
1497   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
1498   * @param  I2Cx I2C Instance.
1499   * @retval State of bit (1 or 0).
1500   */
LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef * I2Cx)1501 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1502 {
1503   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1504 }
1505 
1506 /**
1507   * @brief  Enable STOP detection interrupt.
1508   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
1509   * @param  I2Cx I2C Instance.
1510   * @retval None
1511   */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1512 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1513 {
1514   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1515 }
1516 
1517 /**
1518   * @brief  Disable STOP detection interrupt.
1519   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
1520   * @param  I2Cx I2C Instance.
1521   * @retval None
1522   */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1523 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1524 {
1525   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1526 }
1527 
1528 /**
1529   * @brief  Check if STOP detection interrupt is enabled or disabled.
1530   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
1531   * @param  I2Cx I2C Instance.
1532   * @retval State of bit (1 or 0).
1533   */
LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef * I2Cx)1534 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1535 {
1536   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1537 }
1538 
1539 /**
1540   * @brief  Enable Transfer Complete interrupt.
1541   * @note   Any of these events will generate interrupt :
1542   *         Transfer Complete (TC)
1543   *         Transfer Complete Reload (TCR)
1544   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
1545   * @param  I2Cx I2C Instance.
1546   * @retval None
1547   */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1548 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1549 {
1550   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1551 }
1552 
1553 /**
1554   * @brief  Disable Transfer Complete interrupt.
1555   * @note   Any of these events will generate interrupt :
1556   *         Transfer Complete (TC)
1557   *         Transfer Complete Reload (TCR)
1558   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
1559   * @param  I2Cx I2C Instance.
1560   * @retval None
1561   */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1562 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1563 {
1564   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1565 }
1566 
1567 /**
1568   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
1569   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
1570   * @param  I2Cx I2C Instance.
1571   * @retval State of bit (1 or 0).
1572   */
LL_I2C_IsEnabledIT_TC(const I2C_TypeDef * I2Cx)1573 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1574 {
1575   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1576 }
1577 
1578 /**
1579   * @brief  Enable Error interrupts.
1580   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1581   *         SMBus feature is supported by the I2Cx Instance.
1582   * @note   Any of these errors will generate interrupt :
1583   *         Arbitration Loss (ARLO)
1584   *         Bus Error detection (BERR)
1585   *         Overrun/Underrun (OVR)
1586   *         SMBus Timeout detection (TIMEOUT)
1587   *         SMBus PEC error detection (PECERR)
1588   *         SMBus Alert pin event detection (ALERT)
1589   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
1590   * @param  I2Cx I2C Instance.
1591   * @retval None
1592   */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1593 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1594 {
1595   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1596 }
1597 
1598 /**
1599   * @brief  Disable Error interrupts.
1600   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1601   *         SMBus feature is supported by the I2Cx Instance.
1602   * @note   Any of these errors will generate interrupt :
1603   *         Arbitration Loss (ARLO)
1604   *         Bus Error detection (BERR)
1605   *         Overrun/Underrun (OVR)
1606   *         SMBus Timeout detection (TIMEOUT)
1607   *         SMBus PEC error detection (PECERR)
1608   *         SMBus Alert pin event detection (ALERT)
1609   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
1610   * @param  I2Cx I2C Instance.
1611   * @retval None
1612   */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1613 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1614 {
1615   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1616 }
1617 
1618 /**
1619   * @brief  Check if Error interrupts are enabled or disabled.
1620   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
1621   * @param  I2Cx I2C Instance.
1622   * @retval State of bit (1 or 0).
1623   */
LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef * I2Cx)1624 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1625 {
1626   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1627 }
1628 
1629 /**
1630   * @}
1631   */
1632 
1633 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1634   * @{
1635   */
1636 
1637 /**
1638   * @brief  Indicate the status of Transmit data register empty flag.
1639   * @note   RESET: When next data is written in Transmit data register.
1640   *         SET: When Transmit data register is empty.
1641   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
1642   * @param  I2Cx I2C Instance.
1643   * @retval State of bit (1 or 0).
1644   */
LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef * I2Cx)1645 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1646 {
1647   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1648 }
1649 
1650 /**
1651   * @brief  Indicate the status of Transmit interrupt flag.
1652   * @note   RESET: When next data is written in Transmit data register.
1653   *         SET: When Transmit data register is empty.
1654   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
1655   * @param  I2Cx I2C Instance.
1656   * @retval State of bit (1 or 0).
1657   */
LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef * I2Cx)1658 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1659 {
1660   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1661 }
1662 
1663 /**
1664   * @brief  Indicate the status of Receive data register not empty flag.
1665   * @note   RESET: When Receive data register is read.
1666   *         SET: When the received data is copied in Receive data register.
1667   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
1668   * @param  I2Cx I2C Instance.
1669   * @retval State of bit (1 or 0).
1670   */
LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef * I2Cx)1671 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1672 {
1673   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1674 }
1675 
1676 /**
1677   * @brief  Indicate the status of Address matched flag (slave mode).
1678   * @note   RESET: Clear default value.
1679   *         SET: When the received slave address matched with one of the enabled slave address.
1680   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
1681   * @param  I2Cx I2C Instance.
1682   * @retval State of bit (1 or 0).
1683   */
LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef * I2Cx)1684 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1685 {
1686   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1687 }
1688 
1689 /**
1690   * @brief  Indicate the status of Not Acknowledge received flag.
1691   * @note   RESET: Clear default value.
1692   *         SET: When a NACK is received after a byte transmission.
1693   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
1694   * @param  I2Cx I2C Instance.
1695   * @retval State of bit (1 or 0).
1696   */
LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef * I2Cx)1697 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1698 {
1699   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1700 }
1701 
1702 /**
1703   * @brief  Indicate the status of Stop detection flag.
1704   * @note   RESET: Clear default value.
1705   *         SET: When a Stop condition is detected.
1706   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
1707   * @param  I2Cx I2C Instance.
1708   * @retval State of bit (1 or 0).
1709   */
LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef * I2Cx)1710 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1711 {
1712   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1713 }
1714 
1715 /**
1716   * @brief  Indicate the status of Transfer complete flag (master mode).
1717   * @note   RESET: Clear default value.
1718   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1719   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
1720   * @param  I2Cx I2C Instance.
1721   * @retval State of bit (1 or 0).
1722   */
LL_I2C_IsActiveFlag_TC(const I2C_TypeDef * I2Cx)1723 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1724 {
1725   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1726 }
1727 
1728 /**
1729   * @brief  Indicate the status of Transfer complete flag (master mode).
1730   * @note   RESET: Clear default value.
1731   *         SET: When RELOAD=1 and NBYTES date have been transferred.
1732   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
1733   * @param  I2Cx I2C Instance.
1734   * @retval State of bit (1 or 0).
1735   */
LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef * I2Cx)1736 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1737 {
1738   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1739 }
1740 
1741 /**
1742   * @brief  Indicate the status of Bus error flag.
1743   * @note   RESET: Clear default value.
1744   *         SET: When a misplaced Start or Stop condition is detected.
1745   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
1746   * @param  I2Cx I2C Instance.
1747   * @retval State of bit (1 or 0).
1748   */
LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef * I2Cx)1749 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1750 {
1751   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1752 }
1753 
1754 /**
1755   * @brief  Indicate the status of Arbitration lost flag.
1756   * @note   RESET: Clear default value.
1757   *         SET: When arbitration lost.
1758   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
1759   * @param  I2Cx I2C Instance.
1760   * @retval State of bit (1 or 0).
1761   */
LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef * I2Cx)1762 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1763 {
1764   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1765 }
1766 
1767 /**
1768   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
1769   * @note   RESET: Clear default value.
1770   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1771   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
1772   * @param  I2Cx I2C Instance.
1773   * @retval State of bit (1 or 0).
1774   */
LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef * I2Cx)1775 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1776 {
1777   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1778 }
1779 
1780 /**
1781   * @brief  Indicate the status of SMBus PEC error flag in reception.
1782   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1783   *         SMBus feature is supported by the I2Cx Instance.
1784   * @note   RESET: Clear default value.
1785   *         SET: When the received PEC does not match with the PEC register content.
1786   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
1787   * @param  I2Cx I2C Instance.
1788   * @retval State of bit (1 or 0).
1789   */
LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef * I2Cx)1790 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
1791 {
1792   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1793 }
1794 
1795 /**
1796   * @brief  Indicate the status of SMBus Timeout detection flag.
1797   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1798   *         SMBus feature is supported by the I2Cx Instance.
1799   * @note   RESET: Clear default value.
1800   *         SET: When a timeout or extended clock timeout occurs.
1801   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
1802   * @param  I2Cx I2C Instance.
1803   * @retval State of bit (1 or 0).
1804   */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef * I2Cx)1805 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
1806 {
1807   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1808 }
1809 
1810 /**
1811   * @brief  Indicate the status of SMBus alert flag.
1812   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1813   *         SMBus feature is supported by the I2Cx Instance.
1814   * @note   RESET: Clear default value.
1815   *         SET: When SMBus host configuration, SMBus alert enabled and
1816   *              a falling edge event occurs on SMBA pin.
1817   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
1818   * @param  I2Cx I2C Instance.
1819   * @retval State of bit (1 or 0).
1820   */
LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef * I2Cx)1821 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
1822 {
1823   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1824 }
1825 
1826 /**
1827   * @brief  Indicate the status of Bus Busy flag.
1828   * @note   RESET: Clear default value.
1829   *         SET: When a Start condition is detected.
1830   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
1831   * @param  I2Cx I2C Instance.
1832   * @retval State of bit (1 or 0).
1833   */
LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef * I2Cx)1834 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1835 {
1836   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1837 }
1838 
1839 /**
1840   * @brief  Clear Address Matched flag.
1841   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
1842   * @param  I2Cx I2C Instance.
1843   * @retval None
1844   */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1845 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1846 {
1847   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1848 }
1849 
1850 /**
1851   * @brief  Clear Not Acknowledge flag.
1852   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
1853   * @param  I2Cx I2C Instance.
1854   * @retval None
1855   */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1856 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1857 {
1858   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1859 }
1860 
1861 /**
1862   * @brief  Clear Stop detection flag.
1863   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
1864   * @param  I2Cx I2C Instance.
1865   * @retval None
1866   */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1867 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1868 {
1869   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1870 }
1871 
1872 /**
1873   * @brief  Clear Transmit data register empty flag (TXE).
1874   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
1875   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
1876   * @param  I2Cx I2C Instance.
1877   * @retval None
1878   */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1879 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1880 {
1881   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1882 }
1883 
1884 /**
1885   * @brief  Clear Bus error flag.
1886   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
1887   * @param  I2Cx I2C Instance.
1888   * @retval None
1889   */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1890 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1891 {
1892   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1893 }
1894 
1895 /**
1896   * @brief  Clear Arbitration lost flag.
1897   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
1898   * @param  I2Cx I2C Instance.
1899   * @retval None
1900   */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1901 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1902 {
1903   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1904 }
1905 
1906 /**
1907   * @brief  Clear Overrun/Underrun flag.
1908   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
1909   * @param  I2Cx I2C Instance.
1910   * @retval None
1911   */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1912 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1913 {
1914   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1915 }
1916 
1917 /**
1918   * @brief  Clear SMBus PEC error flag.
1919   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1920   *         SMBus feature is supported by the I2Cx Instance.
1921   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
1922   * @param  I2Cx I2C Instance.
1923   * @retval None
1924   */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1925 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1926 {
1927   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1928 }
1929 
1930 /**
1931   * @brief  Clear SMBus Timeout detection flag.
1932   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1933   *         SMBus feature is supported by the I2Cx Instance.
1934   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
1935   * @param  I2Cx I2C Instance.
1936   * @retval None
1937   */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1938 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1939 {
1940   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1941 }
1942 
1943 /**
1944   * @brief  Clear SMBus Alert flag.
1945   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1946   *         SMBus feature is supported by the I2Cx Instance.
1947   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
1948   * @param  I2Cx I2C Instance.
1949   * @retval None
1950   */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1951 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1952 {
1953   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1954 }
1955 
1956 /**
1957   * @}
1958   */
1959 
1960 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1961   * @{
1962   */
1963 
1964 /**
1965   * @brief  Enable automatic STOP condition generation (master mode).
1966   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1967   *         This bit has no effect in slave mode or when RELOAD bit is set.
1968   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
1969   * @param  I2Cx I2C Instance.
1970   * @retval None
1971   */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1972 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1973 {
1974   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1975 }
1976 
1977 /**
1978   * @brief  Disable automatic STOP condition generation (master mode).
1979   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1980   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
1981   * @param  I2Cx I2C Instance.
1982   * @retval None
1983   */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1984 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1985 {
1986   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1987 }
1988 
1989 /**
1990   * @brief  Check if automatic STOP condition is enabled or disabled.
1991   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
1992   * @param  I2Cx I2C Instance.
1993   * @retval State of bit (1 or 0).
1994   */
LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef * I2Cx)1995 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
1996 {
1997   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1998 }
1999 
2000 /**
2001   * @brief  Enable reload mode (master mode).
2002   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
2003   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
2004   * @param  I2Cx I2C Instance.
2005   * @retval None
2006   */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)2007 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
2008 {
2009   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2010 }
2011 
2012 /**
2013   * @brief  Disable reload mode (master mode).
2014   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
2015   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
2016   * @param  I2Cx I2C Instance.
2017   * @retval None
2018   */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)2019 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
2020 {
2021   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2022 }
2023 
2024 /**
2025   * @brief  Check if reload mode is enabled or disabled.
2026   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
2027   * @param  I2Cx I2C Instance.
2028   * @retval State of bit (1 or 0).
2029   */
LL_I2C_IsEnabledReloadMode(const I2C_TypeDef * I2Cx)2030 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
2031 {
2032   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
2033 }
2034 
2035 /**
2036   * @brief  Configure the number of bytes for transfer.
2037   * @note   Changing these bits when START bit is set is not allowed.
2038   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
2039   * @param  I2Cx I2C Instance.
2040   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
2041   * @retval None
2042   */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)2043 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
2044 {
2045   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
2046 }
2047 
2048 /**
2049   * @brief  Get the number of bytes configured for transfer.
2050   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
2051   * @param  I2Cx I2C Instance.
2052   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
2053   */
LL_I2C_GetTransferSize(const I2C_TypeDef * I2Cx)2054 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
2055 {
2056   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
2057 }
2058 
2059 /**
2060   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
2061             or next received byte.
2062   * @note   Usage in Slave mode only.
2063   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
2064   * @param  I2Cx I2C Instance.
2065   * @param  TypeAcknowledge This parameter can be one of the following values:
2066   *         @arg @ref LL_I2C_ACK
2067   *         @arg @ref LL_I2C_NACK
2068   * @retval None
2069   */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)2070 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
2071 {
2072   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
2073 }
2074 
2075 /**
2076   * @brief  Generate a START or RESTART condition
2077   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
2078   *         This action has no effect when RELOAD is set.
2079   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
2080   * @param  I2Cx I2C Instance.
2081   * @retval None
2082   */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)2083 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
2084 {
2085   SET_BIT(I2Cx->CR2, I2C_CR2_START);
2086 }
2087 
2088 /**
2089   * @brief  Generate a STOP condition after the current byte transfer (master mode).
2090   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
2091   * @param  I2Cx I2C Instance.
2092   * @retval None
2093   */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2094 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2095 {
2096   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2097 }
2098 
2099 /**
2100   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
2101   * @note   The master sends the complete 10bit slave address read sequence :
2102   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2103             in Read direction.
2104   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
2105   * @param  I2Cx I2C Instance.
2106   * @retval None
2107   */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2108 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2109 {
2110   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2111 }
2112 
2113 /**
2114   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
2115   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
2116   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
2117   * @param  I2Cx I2C Instance.
2118   * @retval None
2119   */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2120 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2121 {
2122   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2123 }
2124 
2125 /**
2126   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2127   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
2128   * @param  I2Cx I2C Instance.
2129   * @retval State of bit (1 or 0).
2130   */
LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef * I2Cx)2131 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
2132 {
2133   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2134 }
2135 
2136 /**
2137   * @brief  Configure the transfer direction (master mode).
2138   * @note   Changing these bits when START bit is set is not allowed.
2139   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
2140   * @param  I2Cx I2C Instance.
2141   * @param  TransferRequest This parameter can be one of the following values:
2142   *         @arg @ref LL_I2C_REQUEST_WRITE
2143   *         @arg @ref LL_I2C_REQUEST_READ
2144   * @retval None
2145   */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2146 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2147 {
2148   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2149 }
2150 
2151 /**
2152   * @brief  Get the transfer direction requested (master mode).
2153   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
2154   * @param  I2Cx I2C Instance.
2155   * @retval Returned value can be one of the following values:
2156   *         @arg @ref LL_I2C_REQUEST_WRITE
2157   *         @arg @ref LL_I2C_REQUEST_READ
2158   */
LL_I2C_GetTransferRequest(const I2C_TypeDef * I2Cx)2159 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
2160 {
2161   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2162 }
2163 
2164 /**
2165   * @brief  Configure the slave address for transfer (master mode).
2166   * @note   Changing these bits when START bit is set is not allowed.
2167   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
2168   * @param  I2Cx I2C Instance.
2169   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2170   * @retval None
2171   */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2172 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2173 {
2174   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2175 }
2176 
2177 /**
2178   * @brief  Get the slave address programmed for transfer.
2179   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
2180   * @param  I2Cx I2C Instance.
2181   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2182   */
LL_I2C_GetSlaveAddr(const I2C_TypeDef * I2Cx)2183 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
2184 {
2185   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2186 }
2187 
2188 /**
2189   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2190   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
2191   *         CR2          ADD10         LL_I2C_HandleTransfer\n
2192   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
2193   *         CR2          START         LL_I2C_HandleTransfer\n
2194   *         CR2          STOP          LL_I2C_HandleTransfer\n
2195   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
2196   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
2197   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
2198   *         CR2          HEAD10R       LL_I2C_HandleTransfer
2199   * @param  I2Cx I2C Instance.
2200   * @param  SlaveAddr Specifies the slave address to be programmed.
2201   * @param  SlaveAddrSize This parameter can be one of the following values:
2202   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
2203   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
2204   * @param  TransferSize Specifies the number of bytes to be programmed.
2205   *                       This parameter must be a value between Min_Data=0 and Max_Data=255.
2206   * @param  EndMode This parameter can be one of the following values:
2207   *         @arg @ref LL_I2C_MODE_RELOAD
2208   *         @arg @ref LL_I2C_MODE_AUTOEND
2209   *         @arg @ref LL_I2C_MODE_SOFTEND
2210   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2211   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2212   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2213   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2214   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2215   * @param  Request This parameter can be one of the following values:
2216   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2217   *         @arg @ref LL_I2C_GENERATE_STOP
2218   *         @arg @ref LL_I2C_GENERATE_START_READ
2219   *         @arg @ref LL_I2C_GENERATE_START_WRITE
2220   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2221   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2222   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2223   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2224   * @retval None
2225   */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2226 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2227                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2228 {
2229   /* Declaration of tmp to prevent undefined behavior of volatile usage */
2230   uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
2231                              ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
2232                              (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
2233                              (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
2234 
2235   /* update CR2 register */
2236   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2237              (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2238              I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2239              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2240              tmp);
2241 }
2242 
2243 /**
2244   * @brief  Indicate the value of transfer direction (slave mode).
2245   * @note   RESET: Write transfer, Slave enters in receiver mode.
2246   *         SET: Read transfer, Slave enters in transmitter mode.
2247   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
2248   * @param  I2Cx I2C Instance.
2249   * @retval Returned value can be one of the following values:
2250   *         @arg @ref LL_I2C_DIRECTION_WRITE
2251   *         @arg @ref LL_I2C_DIRECTION_READ
2252   */
LL_I2C_GetTransferDirection(const I2C_TypeDef * I2Cx)2253 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
2254 {
2255   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2256 }
2257 
2258 /**
2259   * @brief  Return the slave matched address.
2260   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
2261   * @param  I2Cx I2C Instance.
2262   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2263   */
LL_I2C_GetAddressMatchCode(const I2C_TypeDef * I2Cx)2264 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
2265 {
2266   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2267 }
2268 
2269 /**
2270   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2271   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2272   *         SMBus feature is supported by the I2Cx Instance.
2273   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2274             or an Address Matched is received.
2275   *         This bit has no effect when RELOAD bit is set.
2276   *         This bit has no effect in device mode when SBC bit is not set.
2277   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
2278   * @param  I2Cx I2C Instance.
2279   * @retval None
2280   */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2281 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2282 {
2283   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2284 }
2285 
2286 /**
2287   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
2288   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2289   *         SMBus feature is supported by the I2Cx Instance.
2290   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
2291   * @param  I2Cx I2C Instance.
2292   * @retval State of bit (1 or 0).
2293   */
LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef * I2Cx)2294 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
2295 {
2296   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2297 }
2298 
2299 /**
2300   * @brief  Get the SMBus Packet Error byte calculated.
2301   * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2302   *         SMBus feature is supported by the I2Cx Instance.
2303   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
2304   * @param  I2Cx I2C Instance.
2305   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2306   */
LL_I2C_GetSMBusPEC(const I2C_TypeDef * I2Cx)2307 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
2308 {
2309   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2310 }
2311 
2312 /**
2313   * @brief  Read Receive Data register.
2314   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
2315   * @param  I2Cx I2C Instance.
2316   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2317   */
LL_I2C_ReceiveData8(const I2C_TypeDef * I2Cx)2318 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
2319 {
2320   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2321 }
2322 
2323 /**
2324   * @brief  Write in Transmit Data Register .
2325   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
2326   * @param  I2Cx I2C Instance.
2327   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
2328   * @retval None
2329   */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2330 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2331 {
2332   WRITE_REG(I2Cx->TXDR, Data);
2333 }
2334 
2335 /**
2336   * @}
2337   */
2338 
2339 #if defined(USE_FULL_LL_DRIVER)
2340 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2341   * @{
2342   */
2343 
2344 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
2345 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
2346 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2347 
2348 
2349 /**
2350   * @}
2351   */
2352 #endif /* USE_FULL_LL_DRIVER */
2353 
2354 /**
2355   * @}
2356   */
2357 
2358 /**
2359   * @}
2360   */
2361 
2362 #endif /* I2C1 || I2C2 || I2C3 */
2363 
2364 /**
2365   * @}
2366   */
2367 
2368 #ifdef __cplusplus
2369 }
2370 #endif
2371 
2372 #endif /* STM32H7RSxx_LL_I2C_H */
2373