1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_I2C_H
21 #define STM32U5xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5) || defined (I2C6)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
53 * @{
54 */
55 #define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__)
56
57 #define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) IS_I2C_GRP2_INSTANCE(__INSTANCE__)
58 /**
59 * @}
60 */
61
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
65 * @{
66 */
67 typedef struct
68 {
69 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
70 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_I2C_SetMode(). */
74
75 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
76 This parameter must be set by referring to the STM32CubeMX Tool and
77 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
78
79 This feature can be modified afterwards using unitary function
80 @ref LL_I2C_SetTiming(). */
81
82 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
83 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
84
85 This feature can be modified afterwards using unitary functions
86 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
87
88 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
89 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
90
91 This feature can be modified afterwards using unitary function
92 @ref LL_I2C_SetDigitalFilter(). */
93
94 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
95 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
96
97 This feature can be modified afterwards using unitary function
98 @ref LL_I2C_SetOwnAddress1(). */
99
100 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
101 match code or next received byte.
102 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
103
104 This feature can be modified afterwards using unitary function
105 @ref LL_I2C_AcknowledgeNextData(). */
106
107 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
108 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
109
110 This feature can be modified afterwards using unitary function
111 @ref LL_I2C_SetOwnAddress1(). */
112 } LL_I2C_InitTypeDef;
113 /**
114 * @}
115 */
116 #endif /*USE_FULL_LL_DRIVER*/
117
118 /* Exported constants --------------------------------------------------------*/
119 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
120 * @{
121 */
122
123 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
124 * @brief Flags defines which can be used with LL_I2C_WriteReg function
125 * @{
126 */
127 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
128 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
129 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
130 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
131 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
132 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
133 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
134 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
135 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
136 /**
137 * @}
138 */
139
140 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
141 * @brief Flags defines which can be used with LL_I2C_ReadReg function
142 * @{
143 */
144 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
145 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
146 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
147 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
148 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
149 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
150 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
151 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
152 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
153 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
154 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
155 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
156 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
157 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
158 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
159 /**
160 * @}
161 */
162
163 /** @defgroup I2C_LL_EC_IT IT Defines
164 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
165 * @{
166 */
167 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
168 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
169 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
170 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
171 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
172 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
173 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
174 /**
175 * @}
176 */
177
178 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
179 * @{
180 */
181 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
182 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
183 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
184 (Default address not acknowledge) */
185 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
186 /**
187 * @}
188 */
189
190 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
191 * @{
192 */
193 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
194 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
195 /**
196 * @}
197 */
198
199 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
200 * @{
201 */
202 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
203 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
209 * @{
210 */
211 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
212 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
213 /**
214 * @}
215 */
216
217 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
218 * @{
219 */
220 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
221 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
222 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
223 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
227 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
228 All Address2 are acknowledged. */
229 /**
230 * @}
231 */
232
233 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
234 * @{
235 */
236 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
237 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
238 /**
239 * @}
240 */
241
242 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
243 * @{
244 */
245 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
246 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
247 /**
248 * @}
249 */
250
251 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
252 * @{
253 */
254 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
255 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
256 /**
257 * @}
258 */
259
260 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
261 * @{
262 */
263 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
264 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
265 with no HW PEC comparison. */
266 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
267 with no HW PEC comparison. */
268 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
269 with HW PEC comparison. */
270 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
271 with HW PEC comparison. */
272 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
273 with HW PEC comparison. */
274 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
275 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
276 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
277 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
278 /**
279 * @}
280 */
281
282 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
283 * @{
284 */
285 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
286 /*!< Don't Generate Stop and Start condition. */
287 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
288 /*!< Generate Stop condition (Size should be set to 0). */
289 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
290 /*!< Generate Start for read request. */
291 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
292 /*!< Generate Start for write request. */
293 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
294 /*!< Generate Restart for read request, slave 7Bit address. */
295 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
296 /*!< Generate Restart for write request, slave 7Bit address. */
297 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
298 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
299 /*!< Generate Restart for read request, slave 10Bit address. */
300 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
301 /*!< Generate Restart for write request, slave 10Bit address.*/
302 /**
303 * @}
304 */
305
306 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
307 * @{
308 */
309 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
310 slave enters receiver mode. */
311 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
312 slave enters transmitter mode.*/
313 /**
314 * @}
315 */
316
317 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
318 * @{
319 */
320 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
321 transmission */
322 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
323 reception */
324 /**
325 * @}
326 */
327
328 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
329 * @{
330 */
331 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
332 SCL low level timeout. */
333 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
334 both SCL and SDA high level timeout.*/
335 /**
336 * @}
337 */
338
339 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
340 * @{
341 */
342 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
343 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
344 enable bit */
345 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
346 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
347 (extended clock) enable bits */
348 /**
349 * @}
350 */
351
352 /** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
353 * @brief I2C Autonomous Trigger selection
354 * @{
355 */
356 #define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */
357 #define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
358
359 #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
360 /*!< HW Trigger signal is GPDMA_CH0_TRG */
361 #define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
362 /*!< HW Trigger signal is GPDMA_CH1_TRG */
363 #define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
364 /*!< HW Trigger signal is GPDMA_CH2_TRG */
365 #define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
366 /*!< HW Trigger signal is GPDMA_CH3_TRG */
367 #define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
368 /*!< HW Trigger signal is EXTI5_TRG */
369 #define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
370 /*!< HW Trigger signal is EXTI9_TRG */
371 #define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
372 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
373 #define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
374 /*!< HW Trigger signal is LPTIM2_CH1_TRG */
375 #define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
376 /*!< HW Trigger signal is COMP1_TRG */
377 #define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
378 /*!< HW Trigger signal is COMP2_TRG */
379 #define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
380 /*!< HW Trigger signal is RTC_ALRA_TRG */
381 #define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
382 /*!< HW Trigger signal is RTC_WUT_TRG */
383
384 #define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
385 /*!< HW Trigger signal is LPDMA_CH0_TRG */
386 #define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
387 /*!< HW Trigger signal is LPDMA_CH1_TRG */
388 #define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
389 /*!< HW Trigger signal is LPDMA_CH2_TRG */
390 #define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
391 /*!< HW Trigger signal is LPDMA_CH3_TRG */
392 #define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
393 /*!< HW Trigger signal is EXTI5_TRG */
394 #define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
395 /*!< HW Trigger signal is EXTI8_TRG */
396 #define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
397 /*!< HW Trigger signal is LPTIM1_CH1_TRG */
398 #define LL_I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
399 /*!< HW Trigger signal is LPTIM3_CH1_TRG */
400 #define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
401 /*!< HW Trigger signal is COMP1_TRG */
402 #define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
403 /*!< HW Trigger signal is COMP2_TRG */
404 #define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
405 /*!< HW Trigger signal is RTC_ALRA_TRG */
406 #define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
407 /*!< HW Trigger signal is RTC_WUT_TRG */
408 /**
409 * @}
410 */
411
412 /** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
413 * @brief I2C Autonomous Trigger Polarity
414 * @{
415 */
416 #define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */
417 #define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */
418 /**
419 * @}
420 */
421
422 /**
423 * @}
424 */
425
426 /* Exported macro ------------------------------------------------------------*/
427 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
428 * @{
429 */
430
431 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
432 * @{
433 */
434
435 /**
436 * @brief Write a value in I2C register
437 * @param __INSTANCE__ I2C Instance
438 * @param __REG__ Register to be written
439 * @param __VALUE__ Value to be written in the register
440 * @retval None
441 */
442 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
443
444 /**
445 * @brief Read a value in I2C register
446 * @param __INSTANCE__ I2C Instance
447 * @param __REG__ Register to be read
448 * @retval Register value
449 */
450 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
451 /**
452 * @}
453 */
454
455 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
456 * @{
457 */
458 /**
459 * @brief Configure the SDA setup, hold time and the SCL high, low period.
460 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
461 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
462 (tscldel = (SCLDEL+1)xtpresc)
463 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
464 (tsdadel = SDADELxtpresc)
465 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
466 (tsclh = (SCLH+1)xtpresc)
467 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
468 (tscll = (SCLL+1)xtpresc)
469 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
470 */
471 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
472 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
473 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
474 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
475 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
476 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
477 /**
478 * @}
479 */
480
481 /**
482 * @}
483 */
484
485 /* Exported functions --------------------------------------------------------*/
486 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
487 * @{
488 */
489
490 /** @defgroup I2C_LL_EF_Configuration Configuration
491 * @{
492 */
493
494 /**
495 * @brief Enable I2C peripheral (PE = 1).
496 * @rmtoll CR1 PE LL_I2C_Enable
497 * @param I2Cx I2C Instance.
498 * @retval None
499 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)500 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
501 {
502 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
503 }
504
505 /**
506 * @brief Disable I2C peripheral (PE = 0).
507 * @note When PE = 0, the I2C SCL and SDA lines are released.
508 * Internal state machines and status bits are put back to their reset value.
509 * When cleared, PE must be kept low for at least 3 APB clock cycles.
510 * @rmtoll CR1 PE LL_I2C_Disable
511 * @param I2Cx I2C Instance.
512 * @retval None
513 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)514 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
515 {
516 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
517 }
518
519 /**
520 * @brief Check if the I2C peripheral is enabled or disabled.
521 * @rmtoll CR1 PE LL_I2C_IsEnabled
522 * @param I2Cx I2C Instance.
523 * @retval State of bit (1 or 0).
524 */
LL_I2C_IsEnabled(const I2C_TypeDef * I2Cx)525 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
526 {
527 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
528 }
529
530 /**
531 * @brief Configure Noise Filters (Analog and Digital).
532 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
533 * The filters can only be programmed when the I2C is disabled (PE = 0).
534 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
535 * CR1 DNF LL_I2C_ConfigFilters
536 * @param I2Cx I2C Instance.
537 * @param AnalogFilter This parameter can be one of the following values:
538 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
539 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
540 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
541 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
542 * This parameter is used to configure the digital noise filter on SDA and SCL input.
543 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
544 * @retval None
545 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)546 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
547 {
548 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
549 }
550
551 /**
552 * @brief Configure Digital Noise Filter.
553 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
554 * This filter can only be programmed when the I2C is disabled (PE = 0).
555 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
556 * @param I2Cx I2C Instance.
557 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
558 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
559 * This parameter is used to configure the digital noise filter on SDA and SCL input.
560 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
561 * @retval None
562 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)563 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
564 {
565 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
566 }
567
568 /**
569 * @brief Get the current Digital Noise Filter configuration.
570 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
571 * @param I2Cx I2C Instance.
572 * @retval Value between Min_Data=0x0 and Max_Data=0xF
573 */
LL_I2C_GetDigitalFilter(const I2C_TypeDef * I2Cx)574 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
575 {
576 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
577 }
578
579 /**
580 * @brief Enable Analog Noise Filter.
581 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
582 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
583 * @param I2Cx I2C Instance.
584 * @retval None
585 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)586 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
587 {
588 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
589 }
590
591 /**
592 * @brief Disable Analog Noise Filter.
593 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
594 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
595 * @param I2Cx I2C Instance.
596 * @retval None
597 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)598 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
599 {
600 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
601 }
602
603 /**
604 * @brief Check if Analog Noise Filter is enabled or disabled.
605 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
606 * @param I2Cx I2C Instance.
607 * @retval State of bit (1 or 0).
608 */
LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef * I2Cx)609 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
610 {
611 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
612 }
613
614 /**
615 * @brief Enable DMA transmission requests.
616 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
617 * @param I2Cx I2C Instance.
618 * @retval None
619 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)620 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
621 {
622 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
623 }
624
625 /**
626 * @brief Disable DMA transmission requests.
627 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
628 * @param I2Cx I2C Instance.
629 * @retval None
630 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)631 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
632 {
633 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
634 }
635
636 /**
637 * @brief Check if DMA transmission requests are enabled or disabled.
638 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
639 * @param I2Cx I2C Instance.
640 * @retval State of bit (1 or 0).
641 */
LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef * I2Cx)642 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
643 {
644 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
645 }
646
647 /**
648 * @brief Enable DMA reception requests.
649 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
650 * @param I2Cx I2C Instance.
651 * @retval None
652 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)653 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
654 {
655 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
656 }
657
658 /**
659 * @brief Disable DMA reception requests.
660 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
661 * @param I2Cx I2C Instance.
662 * @retval None
663 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)664 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
665 {
666 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
667 }
668
669 /**
670 * @brief Check if DMA reception requests are enabled or disabled.
671 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
672 * @param I2Cx I2C Instance.
673 * @retval State of bit (1 or 0).
674 */
LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef * I2Cx)675 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
676 {
677 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
678 }
679
680 /**
681 * @brief Get the data register address used for DMA transfer
682 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
683 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
684 * @param I2Cx I2C Instance
685 * @param Direction This parameter can be one of the following values:
686 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
687 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
688 * @retval Address of data register
689 */
LL_I2C_DMA_GetRegAddr(const I2C_TypeDef * I2Cx,uint32_t Direction)690 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
691 {
692 uint32_t data_reg_addr;
693
694 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
695 {
696 /* return address of TXDR register */
697 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
698 }
699 else
700 {
701 /* return address of RXDR register */
702 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
703 }
704
705 return data_reg_addr;
706 }
707
708 /**
709 * @brief Enable Clock stretching.
710 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
711 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
712 * @param I2Cx I2C Instance.
713 * @retval None
714 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)715 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
716 {
717 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
718 }
719
720 /**
721 * @brief Disable Clock stretching.
722 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
723 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
724 * @param I2Cx I2C Instance.
725 * @retval None
726 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)727 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
728 {
729 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
730 }
731
732 /**
733 * @brief Check if Clock stretching is enabled or disabled.
734 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
735 * @param I2Cx I2C Instance.
736 * @retval State of bit (1 or 0).
737 */
LL_I2C_IsEnabledClockStretching(const I2C_TypeDef * I2Cx)738 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
739 {
740 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
741 }
742
743 /**
744 * @brief Enable hardware byte control in slave mode.
745 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
746 * @param I2Cx I2C Instance.
747 * @retval None
748 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)749 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
750 {
751 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
752 }
753
754 /**
755 * @brief Disable hardware byte control in slave mode.
756 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
757 * @param I2Cx I2C Instance.
758 * @retval None
759 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)760 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
761 {
762 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
763 }
764
765 /**
766 * @brief Check if hardware byte control in slave mode is enabled or disabled.
767 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
768 * @param I2Cx I2C Instance.
769 * @retval State of bit (1 or 0).
770 */
LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef * I2Cx)771 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
772 {
773 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
774 }
775
776 /**
777 * @brief Enable Wakeup from STOP.
778 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
779 * WakeUpFromStop feature is supported by the I2Cx Instance.
780 * @note This bit can only be programmed when Digital Filter is disabled.
781 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
782 * @param I2Cx I2C Instance.
783 * @retval None
784 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)785 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
786 {
787 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
788 }
789
790 /**
791 * @brief Disable Wakeup from STOP.
792 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
793 * WakeUpFromStop feature is supported by the I2Cx Instance.
794 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
795 * @param I2Cx I2C Instance.
796 * @retval None
797 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)798 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
799 {
800 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
801 }
802
803 /**
804 * @brief Check if Wakeup from STOP is enabled or disabled.
805 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
806 * WakeUpFromStop feature is supported by the I2Cx Instance.
807 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
808 * @param I2Cx I2C Instance.
809 * @retval State of bit (1 or 0).
810 */
LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef * I2Cx)811 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
812 {
813 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
814 }
815
816 /**
817 * @brief Enable General Call.
818 * @note When enabled the Address 0x00 is ACKed.
819 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
820 * @param I2Cx I2C Instance.
821 * @retval None
822 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)823 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
824 {
825 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
826 }
827
828 /**
829 * @brief Disable General Call.
830 * @note When disabled the Address 0x00 is NACKed.
831 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
832 * @param I2Cx I2C Instance.
833 * @retval None
834 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)835 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
836 {
837 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
838 }
839
840 /**
841 * @brief Check if General Call is enabled or disabled.
842 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
843 * @param I2Cx I2C Instance.
844 * @retval State of bit (1 or 0).
845 */
LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef * I2Cx)846 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
847 {
848 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
849 }
850
851 /**
852 * @brief Enable I2C Fast Mode Plus (FMP = 1).
853 * @note 20mA I/O drive enable
854 * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
855 * @param I2Cx I2C Instance.
856 * @retval None
857 */
LL_I2C_EnableFastModePlus(I2C_TypeDef * I2Cx)858 __STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
859 {
860 SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
861 }
862
863 /**
864 * @brief Disable I2C Fast Mode Plus (FMP = 0).
865 * @note 20mA I/O drive disable
866 * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
867 * @param I2Cx I2C Instance.
868 * @retval None
869 */
LL_I2C_DisableFastModePlus(I2C_TypeDef * I2Cx)870 __STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
871 {
872 CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
873 }
874
875 /**
876 * @brief Check if the I2C Fast Mode Plus is enabled or disabled.
877 * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
878 * @param I2Cx I2C Instance.
879 * @retval State of bit (1 or 0).
880 */
LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef * I2Cx)881 __STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx)
882 {
883 return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
884 }
885
886 /**
887 * @brief Enable automatic clear of ADDR flag.
888 * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR
889 * @param I2Cx I2C Instance.
890 * @retval None
891 */
LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)892 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
893 {
894 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
895 }
896
897 /**
898 * @brief Disable automatic clear of ADDR flag.
899 * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR
900 * @param I2Cx I2C Instance.
901 * @retval None
902 */
LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)903 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
904 {
905 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
906 }
907
908 /**
909 * @brief Check if the automatic clear of ADDR flag is enabled or disabled.
910 * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR
911 * @param I2Cx I2C Instance.
912 * @retval State of bit (1 or 0).
913 */
LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef * I2Cx)914 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx)
915 {
916 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
917 }
918
919 /**
920 * @brief Enable automatic clear of STOP flag.
921 * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP
922 * @param I2Cx I2C Instance.
923 * @retval None
924 */
LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)925 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
926 {
927 SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
928 }
929
930 /**
931 * @brief Disable automatic clear of STOP flag.
932 * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP
933 * @param I2Cx I2C Instance.
934 * @retval None
935 */
LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)936 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
937 {
938 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
939 }
940
941 /**
942 * @brief Check if the automatic clear of STOP flag is enabled or disabled.
943 * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP
944 * @param I2Cx I2C Instance.
945 * @retval State of bit (1 or 0).
946 */
LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef * I2Cx)947 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx)
948 {
949 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
950 }
951
952 /**
953 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
954 * @note Changing this bit is not allowed, when the START bit is set.
955 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
956 * @param I2Cx I2C Instance.
957 * @param AddressingMode This parameter can be one of the following values:
958 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
959 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
960 * @retval None
961 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)962 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
963 {
964 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
965 }
966
967 /**
968 * @brief Get the Master addressing mode.
969 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
970 * @param I2Cx I2C Instance.
971 * @retval Returned value can be one of the following values:
972 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
973 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
974 */
LL_I2C_GetMasterAddressingMode(const I2C_TypeDef * I2Cx)975 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
976 {
977 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
978 }
979
980 /**
981 * @brief Set the Own Address1.
982 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
983 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
984 * @param I2Cx I2C Instance.
985 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
986 * @param OwnAddrSize This parameter can be one of the following values:
987 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
988 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
989 * @retval None
990 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)991 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
992 {
993 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
994 }
995
996 /**
997 * @brief Enable acknowledge on Own Address1 match address.
998 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
999 * @param I2Cx I2C Instance.
1000 * @retval None
1001 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)1002 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
1003 {
1004 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
1005 }
1006
1007 /**
1008 * @brief Disable acknowledge on Own Address1 match address.
1009 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
1010 * @param I2Cx I2C Instance.
1011 * @retval None
1012 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)1013 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
1014 {
1015 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
1016 }
1017
1018 /**
1019 * @brief Check if Own Address1 acknowledge is enabled or disabled.
1020 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
1021 * @param I2Cx I2C Instance.
1022 * @retval State of bit (1 or 0).
1023 */
LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef * I2Cx)1024 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
1025 {
1026 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
1027 }
1028
1029 /**
1030 * @brief Set the 7bits Own Address2.
1031 * @note This action has no effect if own address2 is enabled.
1032 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
1033 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
1034 * @param I2Cx I2C Instance.
1035 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
1036 * @param OwnAddrMask This parameter can be one of the following values:
1037 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
1038 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
1039 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
1040 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
1041 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
1042 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
1043 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
1044 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
1045 * @retval None
1046 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)1047 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
1048 {
1049 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
1050 }
1051
1052 /**
1053 * @brief Enable acknowledge on Own Address2 match address.
1054 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
1055 * @param I2Cx I2C Instance.
1056 * @retval None
1057 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)1058 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
1059 {
1060 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
1061 }
1062
1063 /**
1064 * @brief Disable acknowledge on Own Address2 match address.
1065 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
1066 * @param I2Cx I2C Instance.
1067 * @retval None
1068 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)1069 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
1070 {
1071 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
1072 }
1073
1074 /**
1075 * @brief Check if Own Address1 acknowledge is enabled or disabled.
1076 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
1077 * @param I2Cx I2C Instance.
1078 * @retval State of bit (1 or 0).
1079 */
LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef * I2Cx)1080 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
1081 {
1082 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
1083 }
1084
1085 /**
1086 * @brief Configure the SDA setup, hold time and the SCL high, low period.
1087 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
1088 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
1089 * @param I2Cx I2C Instance.
1090 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1091 * @note This parameter is computed with the STM32CubeMX Tool.
1092 * @retval None
1093 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)1094 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
1095 {
1096 WRITE_REG(I2Cx->TIMINGR, Timing);
1097 }
1098
1099 /**
1100 * @brief Get the Timing Prescaler setting.
1101 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
1102 * @param I2Cx I2C Instance.
1103 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1104 */
LL_I2C_GetTimingPrescaler(const I2C_TypeDef * I2Cx)1105 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
1106 {
1107 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
1108 }
1109
1110 /**
1111 * @brief Get the SCL low period setting.
1112 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
1113 * @param I2Cx I2C Instance.
1114 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1115 */
LL_I2C_GetClockLowPeriod(const I2C_TypeDef * I2Cx)1116 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
1117 {
1118 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
1119 }
1120
1121 /**
1122 * @brief Get the SCL high period setting.
1123 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
1124 * @param I2Cx I2C Instance.
1125 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1126 */
LL_I2C_GetClockHighPeriod(const I2C_TypeDef * I2Cx)1127 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
1128 {
1129 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
1130 }
1131
1132 /**
1133 * @brief Get the SDA hold time.
1134 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
1135 * @param I2Cx I2C Instance.
1136 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1137 */
LL_I2C_GetDataHoldTime(const I2C_TypeDef * I2Cx)1138 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
1139 {
1140 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
1141 }
1142
1143 /**
1144 * @brief Get the SDA setup time.
1145 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
1146 * @param I2Cx I2C Instance.
1147 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1148 */
LL_I2C_GetDataSetupTime(const I2C_TypeDef * I2Cx)1149 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
1150 {
1151 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
1152 }
1153
1154 /**
1155 * @brief Configure peripheral mode.
1156 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1157 * SMBus feature is supported by the I2Cx Instance.
1158 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
1159 * CR1 SMBDEN LL_I2C_SetMode
1160 * @param I2Cx I2C Instance.
1161 * @param PeripheralMode This parameter can be one of the following values:
1162 * @arg @ref LL_I2C_MODE_I2C
1163 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1164 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1165 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1166 * @retval None
1167 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)1168 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
1169 {
1170 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1171 }
1172
1173 /**
1174 * @brief Get peripheral mode.
1175 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1176 * SMBus feature is supported by the I2Cx Instance.
1177 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1178 * CR1 SMBDEN LL_I2C_GetMode
1179 * @param I2Cx I2C Instance.
1180 * @retval Returned value can be one of the following values:
1181 * @arg @ref LL_I2C_MODE_I2C
1182 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1183 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1184 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1185 */
LL_I2C_GetMode(const I2C_TypeDef * I2Cx)1186 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
1187 {
1188 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1189 }
1190
1191 /**
1192 * @brief Enable SMBus alert (Host or Device mode)
1193 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1194 * SMBus feature is supported by the I2Cx Instance.
1195 * @note SMBus Device mode:
1196 * - SMBus Alert pin is drived low and
1197 * Alert Response Address Header acknowledge is enabled.
1198 * SMBus Host mode:
1199 * - SMBus Alert pin management is supported.
1200 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1201 * @param I2Cx I2C Instance.
1202 * @retval None
1203 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1204 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1205 {
1206 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1207 }
1208
1209 /**
1210 * @brief Disable SMBus alert (Host or Device mode)
1211 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1212 * SMBus feature is supported by the I2Cx Instance.
1213 * @note SMBus Device mode:
1214 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1215 * Alert Response Address Header acknowledge is disabled.
1216 * SMBus Host mode:
1217 * - SMBus Alert pin management is not supported.
1218 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1219 * @param I2Cx I2C Instance.
1220 * @retval None
1221 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1222 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1223 {
1224 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1225 }
1226
1227 /**
1228 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1229 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1230 * SMBus feature is supported by the I2Cx Instance.
1231 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1232 * @param I2Cx I2C Instance.
1233 * @retval State of bit (1 or 0).
1234 */
LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef * I2Cx)1235 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
1236 {
1237 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1238 }
1239
1240 /**
1241 * @brief Enable SMBus Packet Error Calculation (PEC).
1242 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1243 * SMBus feature is supported by the I2Cx Instance.
1244 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1245 * @param I2Cx I2C Instance.
1246 * @retval None
1247 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1248 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1249 {
1250 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1251 }
1252
1253 /**
1254 * @brief Disable SMBus Packet Error Calculation (PEC).
1255 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1256 * SMBus feature is supported by the I2Cx Instance.
1257 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1258 * @param I2Cx I2C Instance.
1259 * @retval None
1260 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1261 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1262 {
1263 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1264 }
1265
1266 /**
1267 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1268 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1269 * SMBus feature is supported by the I2Cx Instance.
1270 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1271 * @param I2Cx I2C Instance.
1272 * @retval State of bit (1 or 0).
1273 */
LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef * I2Cx)1274 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
1275 {
1276 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1277 }
1278
1279 /**
1280 * @brief Configure the SMBus Clock Timeout.
1281 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1282 * SMBus feature is supported by the I2Cx Instance.
1283 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1284 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1285 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1286 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1287 * @param I2Cx I2C Instance.
1288 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1289 * @param TimeoutAMode This parameter can be one of the following values:
1290 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1291 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1292 * @param TimeoutB
1293 * @retval None
1294 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1295 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1296 uint32_t TimeoutB)
1297 {
1298 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1299 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1300 }
1301
1302 /**
1303 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1304 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1305 * SMBus feature is supported by the I2Cx Instance.
1306 * @note These bits can only be programmed when TimeoutA is disabled.
1307 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1308 * @param I2Cx I2C Instance.
1309 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1310 * @retval None
1311 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1312 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1313 {
1314 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1315 }
1316
1317 /**
1318 * @brief Get the SMBus Clock TimeoutA setting.
1319 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1320 * SMBus feature is supported by the I2Cx Instance.
1321 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1322 * @param I2Cx I2C Instance.
1323 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1324 */
LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef * I2Cx)1325 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
1326 {
1327 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1328 }
1329
1330 /**
1331 * @brief Set the SMBus Clock TimeoutA mode.
1332 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1333 * SMBus feature is supported by the I2Cx Instance.
1334 * @note This bit can only be programmed when TimeoutA is disabled.
1335 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1336 * @param I2Cx I2C Instance.
1337 * @param TimeoutAMode This parameter can be one of the following values:
1338 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1339 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1340 * @retval None
1341 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1342 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1343 {
1344 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1345 }
1346
1347 /**
1348 * @brief Get the SMBus Clock TimeoutA mode.
1349 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1350 * SMBus feature is supported by the I2Cx Instance.
1351 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1352 * @param I2Cx I2C Instance.
1353 * @retval Returned value can be one of the following values:
1354 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1355 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1356 */
LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef * I2Cx)1357 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
1358 {
1359 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1360 }
1361
1362 /**
1363 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1364 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1365 * SMBus feature is supported by the I2Cx Instance.
1366 * @note These bits can only be programmed when TimeoutB is disabled.
1367 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1368 * @param I2Cx I2C Instance.
1369 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1370 * @retval None
1371 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1372 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1373 {
1374 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1375 }
1376
1377 /**
1378 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1379 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1380 * SMBus feature is supported by the I2Cx Instance.
1381 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1382 * @param I2Cx I2C Instance.
1383 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1384 */
LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef * I2Cx)1385 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
1386 {
1387 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1388 }
1389
1390 /**
1391 * @brief Enable the SMBus Clock Timeout.
1392 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1393 * SMBus feature is supported by the I2Cx Instance.
1394 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1395 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1396 * @param I2Cx I2C Instance.
1397 * @param ClockTimeout This parameter can be one of the following values:
1398 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1399 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1400 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1401 * @retval None
1402 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1403 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1404 {
1405 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1406 }
1407
1408 /**
1409 * @brief Disable the SMBus Clock Timeout.
1410 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1411 * SMBus feature is supported by the I2Cx Instance.
1412 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1413 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1414 * @param I2Cx I2C Instance.
1415 * @param ClockTimeout This parameter can be one of the following values:
1416 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1417 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1418 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1419 * @retval None
1420 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1421 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1422 {
1423 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1424 }
1425
1426 /**
1427 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1428 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1429 * SMBus feature is supported by the I2Cx Instance.
1430 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1431 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1432 * @param I2Cx I2C Instance.
1433 * @param ClockTimeout This parameter can be one of the following values:
1434 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1435 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1436 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1437 * @retval State of bit (1 or 0).
1438 */
LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1439 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1440 {
1441 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1442 (ClockTimeout)) ? 1UL : 0UL);
1443 }
1444
1445 /**
1446 * @}
1447 */
1448
1449 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1450 * @{
1451 */
1452
1453 /**
1454 * @brief Enable TXIS interrupt.
1455 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1456 * @param I2Cx I2C Instance.
1457 * @retval None
1458 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1459 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1460 {
1461 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1462 }
1463
1464 /**
1465 * @brief Disable TXIS interrupt.
1466 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1467 * @param I2Cx I2C Instance.
1468 * @retval None
1469 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1470 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1471 {
1472 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1473 }
1474
1475 /**
1476 * @brief Check if the TXIS Interrupt is enabled or disabled.
1477 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1478 * @param I2Cx I2C Instance.
1479 * @retval State of bit (1 or 0).
1480 */
LL_I2C_IsEnabledIT_TX(const I2C_TypeDef * I2Cx)1481 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
1482 {
1483 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1484 }
1485
1486 /**
1487 * @brief Enable RXNE interrupt.
1488 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1489 * @param I2Cx I2C Instance.
1490 * @retval None
1491 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1492 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1493 {
1494 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1495 }
1496
1497 /**
1498 * @brief Disable RXNE interrupt.
1499 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1500 * @param I2Cx I2C Instance.
1501 * @retval None
1502 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1503 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1504 {
1505 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1506 }
1507
1508 /**
1509 * @brief Check if the RXNE Interrupt is enabled or disabled.
1510 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1511 * @param I2Cx I2C Instance.
1512 * @retval State of bit (1 or 0).
1513 */
LL_I2C_IsEnabledIT_RX(const I2C_TypeDef * I2Cx)1514 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
1515 {
1516 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1517 }
1518
1519 /**
1520 * @brief Enable Address match interrupt (slave mode only).
1521 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1522 * @param I2Cx I2C Instance.
1523 * @retval None
1524 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1525 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1526 {
1527 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1528 }
1529
1530 /**
1531 * @brief Disable Address match interrupt (slave mode only).
1532 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1533 * @param I2Cx I2C Instance.
1534 * @retval None
1535 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1536 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1537 {
1538 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1539 }
1540
1541 /**
1542 * @brief Check if Address match interrupt is enabled or disabled.
1543 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1544 * @param I2Cx I2C Instance.
1545 * @retval State of bit (1 or 0).
1546 */
LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef * I2Cx)1547 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
1548 {
1549 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Enable Not acknowledge received interrupt.
1554 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1555 * @param I2Cx I2C Instance.
1556 * @retval None
1557 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1558 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1559 {
1560 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1561 }
1562
1563 /**
1564 * @brief Disable Not acknowledge received interrupt.
1565 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1566 * @param I2Cx I2C Instance.
1567 * @retval None
1568 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1569 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1570 {
1571 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1572 }
1573
1574 /**
1575 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1576 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1577 * @param I2Cx I2C Instance.
1578 * @retval State of bit (1 or 0).
1579 */
LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef * I2Cx)1580 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
1581 {
1582 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @brief Enable STOP detection interrupt.
1587 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1588 * @param I2Cx I2C Instance.
1589 * @retval None
1590 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1591 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1592 {
1593 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1594 }
1595
1596 /**
1597 * @brief Disable STOP detection interrupt.
1598 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1599 * @param I2Cx I2C Instance.
1600 * @retval None
1601 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1602 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1603 {
1604 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1605 }
1606
1607 /**
1608 * @brief Check if STOP detection interrupt is enabled or disabled.
1609 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1610 * @param I2Cx I2C Instance.
1611 * @retval State of bit (1 or 0).
1612 */
LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef * I2Cx)1613 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
1614 {
1615 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @brief Enable Transfer Complete interrupt.
1620 * @note Any of these events will generate interrupt :
1621 * Transfer Complete (TC)
1622 * Transfer Complete Reload (TCR)
1623 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1624 * @param I2Cx I2C Instance.
1625 * @retval None
1626 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1627 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1628 {
1629 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1630 }
1631
1632 /**
1633 * @brief Disable Transfer Complete interrupt.
1634 * @note Any of these events will generate interrupt :
1635 * Transfer Complete (TC)
1636 * Transfer Complete Reload (TCR)
1637 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1638 * @param I2Cx I2C Instance.
1639 * @retval None
1640 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1641 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1642 {
1643 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1644 }
1645
1646 /**
1647 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1648 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1649 * @param I2Cx I2C Instance.
1650 * @retval State of bit (1 or 0).
1651 */
LL_I2C_IsEnabledIT_TC(const I2C_TypeDef * I2Cx)1652 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
1653 {
1654 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1655 }
1656
1657 /**
1658 * @brief Enable Error interrupts.
1659 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1660 * SMBus feature is supported by the I2Cx Instance.
1661 * @note Any of these errors will generate interrupt :
1662 * Arbitration Loss (ARLO)
1663 * Bus Error detection (BERR)
1664 * Overrun/Underrun (OVR)
1665 * SMBus Timeout detection (TIMEOUT)
1666 * SMBus PEC error detection (PECERR)
1667 * SMBus Alert pin event detection (ALERT)
1668 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1669 * @param I2Cx I2C Instance.
1670 * @retval None
1671 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1672 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1673 {
1674 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1675 }
1676
1677 /**
1678 * @brief Disable Error interrupts.
1679 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1680 * SMBus feature is supported by the I2Cx Instance.
1681 * @note Any of these errors will generate interrupt :
1682 * Arbitration Loss (ARLO)
1683 * Bus Error detection (BERR)
1684 * Overrun/Underrun (OVR)
1685 * SMBus Timeout detection (TIMEOUT)
1686 * SMBus PEC error detection (PECERR)
1687 * SMBus Alert pin event detection (ALERT)
1688 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1689 * @param I2Cx I2C Instance.
1690 * @retval None
1691 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1692 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1693 {
1694 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1695 }
1696
1697 /**
1698 * @brief Check if Error interrupts are enabled or disabled.
1699 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1700 * @param I2Cx I2C Instance.
1701 * @retval State of bit (1 or 0).
1702 */
LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef * I2Cx)1703 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
1704 {
1705 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1706 }
1707
1708 /**
1709 * @}
1710 */
1711
1712 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1713 * @{
1714 */
1715
1716 /**
1717 * @brief Indicate the status of Transmit data register empty flag.
1718 * @note RESET: When next data is written in Transmit data register.
1719 * SET: When Transmit data register is empty.
1720 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1721 * @param I2Cx I2C Instance.
1722 * @retval State of bit (1 or 0).
1723 */
LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef * I2Cx)1724 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
1725 {
1726 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1727 }
1728
1729 /**
1730 * @brief Indicate the status of Transmit interrupt flag.
1731 * @note RESET: When next data is written in Transmit data register.
1732 * SET: When Transmit data register is empty.
1733 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1734 * @param I2Cx I2C Instance.
1735 * @retval State of bit (1 or 0).
1736 */
LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef * I2Cx)1737 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
1738 {
1739 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1740 }
1741
1742 /**
1743 * @brief Indicate the status of Receive data register not empty flag.
1744 * @note RESET: When Receive data register is read.
1745 * SET: When the received data is copied in Receive data register.
1746 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1747 * @param I2Cx I2C Instance.
1748 * @retval State of bit (1 or 0).
1749 */
LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef * I2Cx)1750 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
1751 {
1752 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1753 }
1754
1755 /**
1756 * @brief Indicate the status of Address matched flag (slave mode).
1757 * @note RESET: Clear default value.
1758 * SET: When the received slave address matched with one of the enabled slave address.
1759 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1760 * @param I2Cx I2C Instance.
1761 * @retval State of bit (1 or 0).
1762 */
LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef * I2Cx)1763 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
1764 {
1765 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1766 }
1767
1768 /**
1769 * @brief Indicate the status of Not Acknowledge received flag.
1770 * @note RESET: Clear default value.
1771 * SET: When a NACK is received after a byte transmission.
1772 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1773 * @param I2Cx I2C Instance.
1774 * @retval State of bit (1 or 0).
1775 */
LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef * I2Cx)1776 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
1777 {
1778 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1779 }
1780
1781 /**
1782 * @brief Indicate the status of Stop detection flag.
1783 * @note RESET: Clear default value.
1784 * SET: When a Stop condition is detected.
1785 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1786 * @param I2Cx I2C Instance.
1787 * @retval State of bit (1 or 0).
1788 */
LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef * I2Cx)1789 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
1790 {
1791 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1792 }
1793
1794 /**
1795 * @brief Indicate the status of Transfer complete flag (master mode).
1796 * @note RESET: Clear default value.
1797 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1798 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1799 * @param I2Cx I2C Instance.
1800 * @retval State of bit (1 or 0).
1801 */
LL_I2C_IsActiveFlag_TC(const I2C_TypeDef * I2Cx)1802 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
1803 {
1804 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1805 }
1806
1807 /**
1808 * @brief Indicate the status of Transfer complete flag (master mode).
1809 * @note RESET: Clear default value.
1810 * SET: When RELOAD=1 and NBYTES date have been transferred.
1811 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1812 * @param I2Cx I2C Instance.
1813 * @retval State of bit (1 or 0).
1814 */
LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef * I2Cx)1815 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
1816 {
1817 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Indicate the status of Bus error flag.
1822 * @note RESET: Clear default value.
1823 * SET: When a misplaced Start or Stop condition is detected.
1824 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1825 * @param I2Cx I2C Instance.
1826 * @retval State of bit (1 or 0).
1827 */
LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef * I2Cx)1828 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
1829 {
1830 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1831 }
1832
1833 /**
1834 * @brief Indicate the status of Arbitration lost flag.
1835 * @note RESET: Clear default value.
1836 * SET: When arbitration lost.
1837 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1838 * @param I2Cx I2C Instance.
1839 * @retval State of bit (1 or 0).
1840 */
LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef * I2Cx)1841 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
1842 {
1843 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1844 }
1845
1846 /**
1847 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1848 * @note RESET: Clear default value.
1849 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1850 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1851 * @param I2Cx I2C Instance.
1852 * @retval State of bit (1 or 0).
1853 */
LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef * I2Cx)1854 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
1855 {
1856 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1857 }
1858
1859 /**
1860 * @brief Indicate the status of SMBus PEC error flag in reception.
1861 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1862 * SMBus feature is supported by the I2Cx Instance.
1863 * @note RESET: Clear default value.
1864 * SET: When the received PEC does not match with the PEC register content.
1865 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1866 * @param I2Cx I2C Instance.
1867 * @retval State of bit (1 or 0).
1868 */
LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef * I2Cx)1869 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
1870 {
1871 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1872 }
1873
1874 /**
1875 * @brief Indicate the status of SMBus Timeout detection flag.
1876 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1877 * SMBus feature is supported by the I2Cx Instance.
1878 * @note RESET: Clear default value.
1879 * SET: When a timeout or extended clock timeout occurs.
1880 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1881 * @param I2Cx I2C Instance.
1882 * @retval State of bit (1 or 0).
1883 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef * I2Cx)1884 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
1885 {
1886 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @brief Indicate the status of SMBus alert flag.
1891 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1892 * SMBus feature is supported by the I2Cx Instance.
1893 * @note RESET: Clear default value.
1894 * SET: When SMBus host configuration, SMBus alert enabled and
1895 * a falling edge event occurs on SMBA pin.
1896 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1897 * @param I2Cx I2C Instance.
1898 * @retval State of bit (1 or 0).
1899 */
LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef * I2Cx)1900 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
1901 {
1902 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1903 }
1904
1905 /**
1906 * @brief Indicate the status of Bus Busy flag.
1907 * @note RESET: Clear default value.
1908 * SET: When a Start condition is detected.
1909 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1910 * @param I2Cx I2C Instance.
1911 * @retval State of bit (1 or 0).
1912 */
LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef * I2Cx)1913 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
1914 {
1915 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1916 }
1917
1918 /**
1919 * @brief Clear Address Matched flag.
1920 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1921 * @param I2Cx I2C Instance.
1922 * @retval None
1923 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1924 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1925 {
1926 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1927 }
1928
1929 /**
1930 * @brief Clear Not Acknowledge flag.
1931 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1932 * @param I2Cx I2C Instance.
1933 * @retval None
1934 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1935 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1936 {
1937 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1938 }
1939
1940 /**
1941 * @brief Clear Stop detection flag.
1942 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1943 * @param I2Cx I2C Instance.
1944 * @retval None
1945 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1946 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1947 {
1948 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1949 }
1950
1951 /**
1952 * @brief Clear Transmit data register empty flag (TXE).
1953 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1954 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1955 * @param I2Cx I2C Instance.
1956 * @retval None
1957 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1958 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1959 {
1960 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1961 }
1962
1963 /**
1964 * @brief Clear Bus error flag.
1965 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1966 * @param I2Cx I2C Instance.
1967 * @retval None
1968 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1969 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1970 {
1971 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1972 }
1973
1974 /**
1975 * @brief Clear Arbitration lost flag.
1976 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1977 * @param I2Cx I2C Instance.
1978 * @retval None
1979 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1980 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1981 {
1982 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1983 }
1984
1985 /**
1986 * @brief Clear Overrun/Underrun flag.
1987 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1988 * @param I2Cx I2C Instance.
1989 * @retval None
1990 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1991 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1992 {
1993 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1994 }
1995
1996 /**
1997 * @brief Clear SMBus PEC error flag.
1998 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1999 * SMBus feature is supported by the I2Cx Instance.
2000 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
2001 * @param I2Cx I2C Instance.
2002 * @retval None
2003 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)2004 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
2005 {
2006 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
2007 }
2008
2009 /**
2010 * @brief Clear SMBus Timeout detection flag.
2011 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2012 * SMBus feature is supported by the I2Cx Instance.
2013 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
2014 * @param I2Cx I2C Instance.
2015 * @retval None
2016 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)2017 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
2018 {
2019 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
2020 }
2021
2022 /**
2023 * @brief Clear SMBus Alert flag.
2024 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2025 * SMBus feature is supported by the I2Cx Instance.
2026 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
2027 * @param I2Cx I2C Instance.
2028 * @retval None
2029 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)2030 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
2031 {
2032 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
2033 }
2034
2035 /**
2036 * @}
2037 */
2038
2039 /** @defgroup I2C_LL_EF_Data_Management Data_Management
2040 * @{
2041 */
2042
2043 /**
2044 * @brief Enable automatic STOP condition generation (master mode).
2045 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
2046 * This bit has no effect in slave mode or when RELOAD bit is set.
2047 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
2048 * @param I2Cx I2C Instance.
2049 * @retval None
2050 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)2051 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
2052 {
2053 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
2054 }
2055
2056 /**
2057 * @brief Disable automatic STOP condition generation (master mode).
2058 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
2059 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
2060 * @param I2Cx I2C Instance.
2061 * @retval None
2062 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)2063 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
2064 {
2065 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
2066 }
2067
2068 /**
2069 * @brief Check if automatic STOP condition is enabled or disabled.
2070 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
2071 * @param I2Cx I2C Instance.
2072 * @retval State of bit (1 or 0).
2073 */
LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef * I2Cx)2074 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
2075 {
2076 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
2077 }
2078
2079 /**
2080 * @brief Enable reload mode (master mode).
2081 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
2082 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
2083 * @param I2Cx I2C Instance.
2084 * @retval None
2085 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)2086 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
2087 {
2088 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2089 }
2090
2091 /**
2092 * @brief Disable reload mode (master mode).
2093 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
2094 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
2095 * @param I2Cx I2C Instance.
2096 * @retval None
2097 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)2098 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
2099 {
2100 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2101 }
2102
2103 /**
2104 * @brief Check if reload mode is enabled or disabled.
2105 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
2106 * @param I2Cx I2C Instance.
2107 * @retval State of bit (1 or 0).
2108 */
LL_I2C_IsEnabledReloadMode(const I2C_TypeDef * I2Cx)2109 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
2110 {
2111 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Configure the number of bytes for transfer.
2116 * @note Changing these bits when START bit is set is not allowed.
2117 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
2118 * @param I2Cx I2C Instance.
2119 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
2120 * @retval None
2121 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)2122 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
2123 {
2124 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
2125 }
2126
2127 /**
2128 * @brief Get the number of bytes configured for transfer.
2129 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
2130 * @param I2Cx I2C Instance.
2131 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
2132 */
LL_I2C_GetTransferSize(const I2C_TypeDef * I2Cx)2133 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
2134 {
2135 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
2136 }
2137
2138 /**
2139 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
2140 or next received byte.
2141 * @note Usage in Slave mode only.
2142 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
2143 * @param I2Cx I2C Instance.
2144 * @param TypeAcknowledge This parameter can be one of the following values:
2145 * @arg @ref LL_I2C_ACK
2146 * @arg @ref LL_I2C_NACK
2147 * @retval None
2148 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)2149 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
2150 {
2151 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
2152 }
2153
2154 /**
2155 * @brief Generate a START or RESTART condition
2156 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
2157 * This action has no effect when RELOAD is set.
2158 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
2159 * @param I2Cx I2C Instance.
2160 * @retval None
2161 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)2162 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
2163 {
2164 SET_BIT(I2Cx->CR2, I2C_CR2_START);
2165 }
2166
2167 /**
2168 * @brief Generate a STOP condition after the current byte transfer (master mode).
2169 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
2170 * @param I2Cx I2C Instance.
2171 * @retval None
2172 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2173 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2174 {
2175 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2176 }
2177
2178 /**
2179 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2180 * @note The master sends the complete 10bit slave address read sequence :
2181 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2182 in Read direction.
2183 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2184 * @param I2Cx I2C Instance.
2185 * @retval None
2186 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2187 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2188 {
2189 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2190 }
2191
2192 /**
2193 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2194 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2195 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2196 * @param I2Cx I2C Instance.
2197 * @retval None
2198 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2199 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2200 {
2201 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2202 }
2203
2204 /**
2205 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2206 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2207 * @param I2Cx I2C Instance.
2208 * @retval State of bit (1 or 0).
2209 */
LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef * I2Cx)2210 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
2211 {
2212 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2213 }
2214
2215 /**
2216 * @brief Configure the transfer direction (master mode).
2217 * @note Changing these bits when START bit is set is not allowed.
2218 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2219 * @param I2Cx I2C Instance.
2220 * @param TransferRequest This parameter can be one of the following values:
2221 * @arg @ref LL_I2C_REQUEST_WRITE
2222 * @arg @ref LL_I2C_REQUEST_READ
2223 * @retval None
2224 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2225 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2226 {
2227 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2228 }
2229
2230 /**
2231 * @brief Get the transfer direction requested (master mode).
2232 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2233 * @param I2Cx I2C Instance.
2234 * @retval Returned value can be one of the following values:
2235 * @arg @ref LL_I2C_REQUEST_WRITE
2236 * @arg @ref LL_I2C_REQUEST_READ
2237 */
LL_I2C_GetTransferRequest(const I2C_TypeDef * I2Cx)2238 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
2239 {
2240 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2241 }
2242
2243 /**
2244 * @brief Configure the slave address for transfer (master mode).
2245 * @note Changing these bits when START bit is set is not allowed.
2246 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2247 * @param I2Cx I2C Instance.
2248 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2249 * @retval None
2250 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2251 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2252 {
2253 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2254 }
2255
2256 /**
2257 * @brief Get the slave address programmed for transfer.
2258 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2259 * @param I2Cx I2C Instance.
2260 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2261 */
LL_I2C_GetSlaveAddr(const I2C_TypeDef * I2Cx)2262 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
2263 {
2264 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2265 }
2266
2267 /**
2268 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2269 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2270 * CR2 ADD10 LL_I2C_HandleTransfer\n
2271 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2272 * CR2 START LL_I2C_HandleTransfer\n
2273 * CR2 STOP LL_I2C_HandleTransfer\n
2274 * CR2 RELOAD LL_I2C_HandleTransfer\n
2275 * CR2 NBYTES LL_I2C_HandleTransfer\n
2276 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2277 * CR2 HEAD10R LL_I2C_HandleTransfer
2278 * @param I2Cx I2C Instance.
2279 * @param SlaveAddr Specifies the slave address to be programmed.
2280 * @param SlaveAddrSize This parameter can be one of the following values:
2281 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2282 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2283 * @param TransferSize Specifies the number of bytes to be programmed.
2284 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2285 * @param EndMode This parameter can be one of the following values:
2286 * @arg @ref LL_I2C_MODE_RELOAD
2287 * @arg @ref LL_I2C_MODE_AUTOEND
2288 * @arg @ref LL_I2C_MODE_SOFTEND
2289 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2290 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2291 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2292 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2293 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2294 * @param Request This parameter can be one of the following values:
2295 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2296 * @arg @ref LL_I2C_GENERATE_STOP
2297 * @arg @ref LL_I2C_GENERATE_START_READ
2298 * @arg @ref LL_I2C_GENERATE_START_WRITE
2299 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2300 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2301 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2302 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2303 * @retval None
2304 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2305 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2306 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2307 {
2308 /* Declaration of tmp to prevent undefined behavior of volatile usage */
2309 uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
2310 ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
2311 (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
2312 (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
2313
2314 /* update CR2 register */
2315 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2316 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2317 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2318 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2319 tmp);
2320 }
2321
2322 /**
2323 * @brief Indicate the value of transfer direction (slave mode).
2324 * @note RESET: Write transfer, Slave enters in receiver mode.
2325 * SET: Read transfer, Slave enters in transmitter mode.
2326 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2327 * @param I2Cx I2C Instance.
2328 * @retval Returned value can be one of the following values:
2329 * @arg @ref LL_I2C_DIRECTION_WRITE
2330 * @arg @ref LL_I2C_DIRECTION_READ
2331 */
LL_I2C_GetTransferDirection(const I2C_TypeDef * I2Cx)2332 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
2333 {
2334 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2335 }
2336
2337 /**
2338 * @brief Return the slave matched address.
2339 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2340 * @param I2Cx I2C Instance.
2341 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2342 */
LL_I2C_GetAddressMatchCode(const I2C_TypeDef * I2Cx)2343 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
2344 {
2345 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2346 }
2347
2348 /**
2349 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2350 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2351 * SMBus feature is supported by the I2Cx Instance.
2352 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2353 or an Address Matched is received.
2354 * This bit has no effect when RELOAD bit is set.
2355 * This bit has no effect in device mode when SBC bit is not set.
2356 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2357 * @param I2Cx I2C Instance.
2358 * @retval None
2359 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2360 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2361 {
2362 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2363 }
2364
2365 /**
2366 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2367 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2368 * SMBus feature is supported by the I2Cx Instance.
2369 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2370 * @param I2Cx I2C Instance.
2371 * @retval State of bit (1 or 0).
2372 */
LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef * I2Cx)2373 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
2374 {
2375 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2376 }
2377
2378 /**
2379 * @brief Get the SMBus Packet Error byte calculated.
2380 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2381 * SMBus feature is supported by the I2Cx Instance.
2382 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2383 * @param I2Cx I2C Instance.
2384 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2385 */
LL_I2C_GetSMBusPEC(const I2C_TypeDef * I2Cx)2386 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
2387 {
2388 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2389 }
2390
2391 /**
2392 * @brief Read Receive Data register.
2393 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2394 * @param I2Cx I2C Instance.
2395 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2396 */
LL_I2C_ReceiveData8(const I2C_TypeDef * I2Cx)2397 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
2398 {
2399 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2400 }
2401
2402 /**
2403 * @brief Write in Transmit Data Register .
2404 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2405 * @param I2Cx I2C Instance.
2406 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2407 * @retval None
2408 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2409 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2410 {
2411 WRITE_REG(I2Cx->TXDR, Data);
2412 }
2413
2414 /**
2415 * @}
2416 */
2417
2418 /** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
2419 * @{
2420 */
2421
2422 /**
2423 * @brief Enable Selected Trigger
2424 * @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger
2425 * @param I2Cx I2C Instance.
2426 * @retval None
2427 */
LL_I2C_Enable_SelectedTrigger(I2C_TypeDef * I2Cx)2428 __STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx)
2429 {
2430 SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
2431 }
2432
2433 /**
2434 * @brief Disable Selected Trigger
2435 * @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger
2436 * @param I2Cx I2C Instance.
2437 * @retval None
2438 */
LL_I2C_Disable_SelectedTrigger(I2C_TypeDef * I2Cx)2439 __STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx)
2440 {
2441 CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
2442 }
2443
2444 /**
2445 * @brief Indicate if selected Trigger is disabled or enabled
2446 * @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger
2447 * @param I2Cx I2C Instance.
2448 * @retval State of bit (1 or 0).
2449 */
LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef * I2Cx)2450 __STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef *I2Cx)
2451 {
2452 return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL);
2453 }
2454
2455 /**
2456 * @brief Set the trigger polarity
2457 * @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity
2458 * @param I2Cx I2C Instance.
2459 * @param Polarity This parameter can be one of the following values:
2460 * @arg @ref LL_I2C_TRIG_POLARITY_RISING
2461 * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
2462 * @retval None
2463 */
LL_I2C_SetTriggerPolarity(I2C_TypeDef * I2Cx,uint32_t Polarity)2464 __STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity)
2465 {
2466 MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity);
2467 }
2468
2469 /**
2470 * @brief Get the trigger polarity
2471 * @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity
2472 * @param I2Cx I2C Instance.
2473 * @retval Returned value can be one of the following values:
2474 * @arg @ref LL_I2C_TRIG_POLARITY_RISING
2475 * @arg @ref LL_I2C_TRIG_POLARITY_FALLING
2476 */
LL_I2C_GetTriggerPolarity(const I2C_TypeDef * I2Cx)2477 __STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(const I2C_TypeDef *I2Cx)
2478 {
2479 return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL));
2480 }
2481
2482 /**
2483 * @brief Set the selected trigger
2484 * @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger
2485 * @param I2Cx I2C Instance.
2486 * @param Trigger This parameter can be one of the following values:
2487 * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
2488 * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
2489 * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
2490 * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
2491 * @arg @ref LL_I2C_GRP1_EXTI5_TRG
2492 * @arg @ref LL_I2C_GRP1_EXTI9_TRG
2493 * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
2494 * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
2495 * @arg @ref LL_I2C_GRP1_COMP1_TRG
2496 * @arg @ref LL_I2C_GRP1_COMP2_TRG
2497 * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
2498 * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
2499 * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
2500 * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
2501 * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
2502 * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
2503 * @arg @ref LL_I2C_GRP2_EXTI5_TRG
2504 * @arg @ref LL_I2C_GRP2_EXTI8_TRG
2505 * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
2506 * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
2507 * @arg @ref LL_I2C_GRP2_COMP1_TRG
2508 * @arg @ref LL_I2C_GRP2_COMP2_TRG
2509 * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
2510 * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
2511 * @retval None
2512 */
LL_I2C_SetSelectedTrigger(I2C_TypeDef * I2Cx,uint32_t Trigger)2513 __STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger)
2514 {
2515 MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk));
2516 }
2517
2518 /**
2519 * @brief Get the selected trigger
2520 * @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger
2521 * @param I2Cx I2C Instance.
2522 * @retval Returned value can be one of the following values:
2523 * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
2524 * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
2525 * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
2526 * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
2527 * @arg @ref LL_I2C_GRP1_EXTI5_TRG
2528 * @arg @ref LL_I2C_GRP1_EXTI9_TRG
2529 * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
2530 * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
2531 * @arg @ref LL_I2C_GRP1_COMP1_TRG
2532 * @arg @ref LL_I2C_GRP1_COMP2_TRG
2533 * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
2534 * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
2535 * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
2536 * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
2537 * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
2538 * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
2539 * @arg @ref LL_I2C_GRP2_EXTI5_TRG
2540 * @arg @ref LL_I2C_GRP2_EXTI8_TRG
2541 * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
2542 * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
2543 * @arg @ref LL_I2C_GRP2_COMP1_TRG
2544 * @arg @ref LL_I2C_GRP2_COMP2_TRG
2545 * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
2546 * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
2547 */
LL_I2C_GetSelectedTrigger(const I2C_TypeDef * I2Cx)2548 __STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(const I2C_TypeDef *I2Cx)
2549 {
2550 if (IS_LL_I2C_GRP2_INSTANCE(I2Cx))
2551 {
2552 return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2));
2553 }
2554 else
2555 {
2556 return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1));
2557 }
2558 }
2559
2560 /**
2561 * @}
2562 */
2563
2564 #if defined(USE_FULL_LL_DRIVER)
2565 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2566 * @{
2567 */
2568
2569 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
2570 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
2571 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2572
2573
2574 /**
2575 * @}
2576 */
2577 #endif /* USE_FULL_LL_DRIVER */
2578
2579 /**
2580 * @}
2581 */
2582
2583 /**
2584 * @}
2585 */
2586
2587 #endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 || I2C6 */
2588
2589 /**
2590 * @}
2591 */
2592
2593 #ifdef __cplusplus
2594 }
2595 #endif
2596
2597 #endif /* STM32U5xx_LL_I2C_H */
2598
