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Searched refs:I2C_CR1_ERRIE (Results 1 – 25 of 274) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_i2c.h160 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1218 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1233 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1244 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
Dstm32wlxx_hal_smbus.h366 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1603 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1623 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1634 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
Dstm32l0xx_hal_smbus.h366 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1504 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1524 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1535 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
Dstm32f0xx_hal_smbus.h364 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1504 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1524 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1535 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1462 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1482 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1493 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1462 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1482 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1493 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_i2c.h164 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1595 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1615 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1626 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1603 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1623 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1634 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
Dstm32n6xx_hal_smbus.h363 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_i2c.h172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1502 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1522 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1533 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_i2c.h173 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1674 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1694 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1705 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_i2c.h175 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable …
1686 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_EnableIT_ERR()
1706 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); in LL_I2C_DisableIT_ERR()
1717 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); in LL_I2C_IsEnabledIT_ERR()
Dstm32wbaxx_hal_smbus.h365 #define SMBUS_IT_ERRI I2C_CR1_ERRIE

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