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Searched refs:GTZC_CFGR3_GPU2D_Pos (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h285 #define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h22296 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
22297 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
22514 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
22666 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
22818 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23036 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23254 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u599xx.h24477 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
24478 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
24689 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
24839 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
24989 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25201 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25413 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5g7xx.h22912 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
22913 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
23140 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23298 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23456 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23684 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
23912 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5f9xx.h25439 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
25440 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
25659 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25813 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25967 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26187 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26407 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5a9xx.h25093 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
25094 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
25315 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25471 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25627 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
25849 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26071 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
Dstm32u5g9xx.h26055 #define GTZC_CFGR3_GPU2D_Pos (23U) macro
26056 #define GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos)
26285 #define GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26445 #define GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26605 #define GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
26835 #define GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos
27065 #define GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos