Searched refs:GTZC_CFGR3_GFXMMU_REG_Msk (Results 1 – 6 of 6) sorted by relevance
22301 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro22519 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk22671 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk22823 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23041 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23259 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
24482 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro24694 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk24844 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk24994 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25206 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25418 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
22917 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro23145 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23303 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23461 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23689 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk23917 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
25444 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro25664 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25818 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25972 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26192 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26412 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
25098 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro25320 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25476 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25632 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk25854 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26076 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
26060 #define GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) macro26290 #define GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26450 #define GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26610 #define GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk26840 #define GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk27070 #define GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk
