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Searched refs:GTZC_CFGR2_SPI1_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_gtzc.h171 #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h260 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h224 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15795 #define GTZC_CFGR2_SPI1_Pos (9U) macro
15796 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
15946 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16053 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16159 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16309 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16459 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h562xx.h17125 #define GTZC_CFGR2_SPI1_Pos (9U) macro
17126 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
17314 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17459 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17603 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17791 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17979 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h533xx.h16344 #define GTZC_CFGR2_SPI1_Pos (9U) macro
16345 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
16503 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16616 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16728 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
16886 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
17044 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h573xx.h19772 #define GTZC_CFGR2_SPI1_Pos (9U) macro
19773 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19975 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20132 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20288 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20490 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20692 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h563xx.h19223 #define GTZC_CFGR2_SPI1_Pos (9U) macro
19224 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19418 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19569 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19719 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19913 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20107 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32h503xx.h10875 #define GTZC_CFGR2_SPI1_Pos (9U) macro
10876 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
10976 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18417 #define GTZC_CFGR2_SPI1_Pos (1U) macro
18418 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
18589 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18709 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18829 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18999 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19169 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u535xx.h17865 #define GTZC_CFGR2_SPI1_Pos (1U) macro
17866 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
18029 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18143 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18257 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18419 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
18581 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u575xx.h19462 #define GTZC_CFGR2_SPI1_Pos (1U) macro
19463 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
19648 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19778 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
19908 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20094 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20280 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u585xx.h20072 #define GTZC_CFGR2_SPI1_Pos (1U) macro
20073 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
20268 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20404 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20540 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20736 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20932 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u595xx.h20641 #define GTZC_CFGR2_SPI1_Pos (1U) macro
20642 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
20843 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
20983 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21123 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21325 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21527 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5a5xx.h21251 #define GTZC_CFGR2_SPI1_Pos (1U) macro
21252 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
21463 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21609 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21755 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
21967 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
22179 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5f7xx.h22234 #define GTZC_CFGR2_SPI1_Pos (1U) macro
22235 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
22452 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
22604 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
22756 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
22974 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
23192 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u599xx.h24415 #define GTZC_CFGR2_SPI1_Pos (1U) macro
24416 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
24627 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
24777 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
24927 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25139 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25351 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5g7xx.h22844 #define GTZC_CFGR2_SPI1_Pos (1U) macro
22845 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
23072 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
23230 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
23388 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
23616 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
23844 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5f9xx.h25375 #define GTZC_CFGR2_SPI1_Pos (1U) macro
25376 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
25595 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25749 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25903 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26123 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26343 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5a9xx.h25025 #define GTZC_CFGR2_SPI1_Pos (1U) macro
25026 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
25247 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25403 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25559 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
25781 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26003 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
Dstm32u5g9xx.h25985 #define GTZC_CFGR2_SPI1_Pos (1U) macro
25986 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
26215 #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26375 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26535 #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26765 #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
26995 #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h5640 #define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos macro
5641 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
Dstm32wba54xx.h5823 #define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos macro
5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
Dstm32wba5mxx.h5823 #define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos macro
5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)
Dstm32wba55xx.h5823 #define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos macro
5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos)