Home
last modified time | relevance | path

Searched refs:GTZC_CFGR2_SPI1_Msk (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15796 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
15947 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16054 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16160 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16310 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16460 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32h562xx.h17126 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
17315 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
17460 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
17604 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
17792 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
17980 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32h533xx.h16345 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
16504 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16617 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16729 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
16887 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
17045 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32h573xx.h19773 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
19976 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20133 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20289 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20491 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20693 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32h563xx.h19224 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
19419 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19570 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19720 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19914 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20108 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32h503xx.h10876 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
10977 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18418 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
18590 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18710 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18830 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19000 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19170 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u535xx.h17866 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
18030 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18144 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18258 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18420 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
18582 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u575xx.h19463 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
19649 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19779 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
19909 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20095 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20281 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u585xx.h20073 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
20269 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20405 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20541 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20737 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20933 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u595xx.h20642 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
20844 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
20984 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21124 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21326 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21528 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5a5xx.h21252 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
21464 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21610 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21756 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
21968 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
22180 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5f7xx.h22235 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
22453 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
22605 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
22757 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
22975 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
23193 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u599xx.h24416 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
24628 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
24778 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
24928 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25140 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25352 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5g7xx.h22845 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
23073 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
23231 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
23389 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
23617 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
23845 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5f9xx.h25376 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
25596 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25750 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25904 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26124 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26344 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5a9xx.h25026 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
25248 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25404 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25560 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
25782 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26004 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
Dstm32u5g9xx.h25986 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
26216 #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26376 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26536 #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26766 #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
26996 #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h5641 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
Dstm32wba54xx.h5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
Dstm32wba5mxx.h5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro
Dstm32wba55xx.h5824 #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) macro