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Searched refs:GTZC_CFGR1_TIM5_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h173 #define GTZC_PERIPH_TIM5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h189 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h193 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos)
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16409 #define GTZC_CFGR1_TIM5_Pos (3U) macro
16410 #define GTZC_CFGR1_TIM5_Msk ( 0x01UL << GTZC_CFGR1_TIM5_Pos )
16549 #define GTZC_TZSC_SECCFGR1_TIM5SEC_Pos GTZC_CFGR1_TIM5_Pos
16651 #define GTZC_TZSC_PRIVCFGR1_TIM5PRIV_Pos GTZC_CFGR1_TIM5_Pos
16753 #define GTZC_TZIC_IER1_TIM5IE_Pos GTZC_CFGR1_TIM5_Pos
16893 #define GTZC_TZIC_SR1_TIM5F_Pos GTZC_CFGR1_TIM5_Pos
17033 #define GTZC_TZIC_FCR1_TIM5FC_Pos GTZC_CFGR1_TIM5_Pos
Dstm32l562xx.h17148 #define GTZC_CFGR1_TIM5_Pos (3U) macro
17149 #define GTZC_CFGR1_TIM5_Msk ( 0x01UL << GTZC_CFGR1_TIM5_Pos )
17294 #define GTZC_TZSC_SECCFGR1_TIM5SEC_Pos GTZC_CFGR1_TIM5_Pos
17400 #define GTZC_TZSC_PRIVCFGR1_TIM5PRIV_Pos GTZC_CFGR1_TIM5_Pos
17506 #define GTZC_TZIC_IER1_TIM5IE_Pos GTZC_CFGR1_TIM5_Pos
17652 #define GTZC_TZIC_SR1_TIM5F_Pos GTZC_CFGR1_TIM5_Pos
17798 #define GTZC_TZIC_FCR1_TIM5FC_Pos GTZC_CFGR1_TIM5_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15743 #define GTZC_CFGR1_TIM5_Pos (3U) macro
15744 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
15894 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16001 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16107 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16257 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16407 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32h562xx.h17059 #define GTZC_CFGR1_TIM5_Pos (3U) macro
17060 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
17248 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
17393 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
17537 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
17725 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
17913 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32h533xx.h16292 #define GTZC_CFGR1_TIM5_Pos (3U) macro
16293 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
16451 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16564 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16676 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16834 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
16992 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32h573xx.h19704 #define GTZC_CFGR1_TIM5_Pos (3U) macro
19705 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
19907 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20064 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20220 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20422 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20624 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32h563xx.h19155 #define GTZC_CFGR1_TIM5_Pos (3U) macro
19156 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
19350 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19501 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19651 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19845 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20039 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18383 #define GTZC_CFGR1_TIM5_Pos (3U) macro
18384 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
18555 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18675 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18795 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18965 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19135 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u535xx.h17831 #define GTZC_CFGR1_TIM5_Pos (3U) macro
17832 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
17995 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18109 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18223 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18385 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
18547 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u575xx.h19424 #define GTZC_CFGR1_TIM5_Pos (3U) macro
19425 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
19610 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19740 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
19870 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20056 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20242 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u585xx.h20034 #define GTZC_CFGR1_TIM5_Pos (3U) macro
20035 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
20230 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20366 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20502 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20698 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20894 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u595xx.h20597 #define GTZC_CFGR1_TIM5_Pos (3U) macro
20598 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
20799 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
20939 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21079 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21281 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21483 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5a5xx.h21207 #define GTZC_CFGR1_TIM5_Pos (3U) macro
21208 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
21419 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21565 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21711 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
21923 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
22135 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5f7xx.h22190 #define GTZC_CFGR1_TIM5_Pos (3U) macro
22191 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
22408 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
22560 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
22712 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
22930 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
23148 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u599xx.h24371 #define GTZC_CFGR1_TIM5_Pos (3U) macro
24372 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
24583 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
24733 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
24883 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25095 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25307 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5g7xx.h22800 #define GTZC_CFGR1_TIM5_Pos (3U) macro
22801 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
23028 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
23186 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
23344 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
23572 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
23800 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5f9xx.h25331 #define GTZC_CFGR1_TIM5_Pos (3U) macro
25332 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
25551 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25705 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25859 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26079 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26299 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5a9xx.h24981 #define GTZC_CFGR1_TIM5_Pos (3U) macro
24982 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
25203 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25359 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25515 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25737 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
25959 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
Dstm32u5g9xx.h25941 #define GTZC_CFGR1_TIM5_Pos (3U) macro
25942 #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos)
26171 #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26331 #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26491 #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26721 #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos
26951 #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos