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Searched refs:GTZC_CFGR1_TIM4_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h172 #define GTZC_PERIPH_TIM4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h186 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h192 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos)
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16411 #define GTZC_CFGR1_TIM4_Pos (2U) macro
16412 #define GTZC_CFGR1_TIM4_Msk ( 0x01UL << GTZC_CFGR1_TIM4_Pos )
16551 #define GTZC_TZSC_SECCFGR1_TIM4SEC_Pos GTZC_CFGR1_TIM4_Pos
16653 #define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Pos GTZC_CFGR1_TIM4_Pos
16755 #define GTZC_TZIC_IER1_TIM4IE_Pos GTZC_CFGR1_TIM4_Pos
16895 #define GTZC_TZIC_SR1_TIM4F_Pos GTZC_CFGR1_TIM4_Pos
17035 #define GTZC_TZIC_FCR1_TIM4FC_Pos GTZC_CFGR1_TIM4_Pos
Dstm32l562xx.h17150 #define GTZC_CFGR1_TIM4_Pos (2U) macro
17151 #define GTZC_CFGR1_TIM4_Msk ( 0x01UL << GTZC_CFGR1_TIM4_Pos )
17296 #define GTZC_TZSC_SECCFGR1_TIM4SEC_Pos GTZC_CFGR1_TIM4_Pos
17402 #define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Pos GTZC_CFGR1_TIM4_Pos
17508 #define GTZC_TZIC_IER1_TIM4IE_Pos GTZC_CFGR1_TIM4_Pos
17654 #define GTZC_TZIC_SR1_TIM4F_Pos GTZC_CFGR1_TIM4_Pos
17800 #define GTZC_TZIC_FCR1_TIM4FC_Pos GTZC_CFGR1_TIM4_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15741 #define GTZC_CFGR1_TIM4_Pos (2U) macro
15742 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
15892 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
15999 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16105 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16255 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16405 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32h562xx.h17057 #define GTZC_CFGR1_TIM4_Pos (2U) macro
17058 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
17246 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
17391 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
17535 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
17723 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
17911 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32h533xx.h16290 #define GTZC_CFGR1_TIM4_Pos (2U) macro
16291 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
16449 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16562 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16674 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16832 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
16990 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32h573xx.h19702 #define GTZC_CFGR1_TIM4_Pos (2U) macro
19703 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
19905 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20062 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20218 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20420 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20622 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32h563xx.h19153 #define GTZC_CFGR1_TIM4_Pos (2U) macro
19154 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
19348 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19499 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19649 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19843 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20037 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18381 #define GTZC_CFGR1_TIM4_Pos (2U) macro
18382 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
18553 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18673 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18793 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18963 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19133 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u535xx.h17829 #define GTZC_CFGR1_TIM4_Pos (2U) macro
17830 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
17993 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18107 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18221 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18383 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
18545 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u575xx.h19422 #define GTZC_CFGR1_TIM4_Pos (2U) macro
19423 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
19608 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19738 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
19868 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20054 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20240 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u585xx.h20032 #define GTZC_CFGR1_TIM4_Pos (2U) macro
20033 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
20228 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20364 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20500 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20696 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20892 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u595xx.h20595 #define GTZC_CFGR1_TIM4_Pos (2U) macro
20596 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
20797 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
20937 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21077 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21279 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21481 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5a5xx.h21205 #define GTZC_CFGR1_TIM4_Pos (2U) macro
21206 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
21417 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21563 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21709 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
21921 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
22133 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5f7xx.h22188 #define GTZC_CFGR1_TIM4_Pos (2U) macro
22189 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
22406 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
22558 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
22710 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
22928 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
23146 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u599xx.h24369 #define GTZC_CFGR1_TIM4_Pos (2U) macro
24370 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
24581 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
24731 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
24881 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25093 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25305 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5g7xx.h22798 #define GTZC_CFGR1_TIM4_Pos (2U) macro
22799 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
23026 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
23184 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
23342 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
23570 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
23798 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5f9xx.h25329 #define GTZC_CFGR1_TIM4_Pos (2U) macro
25330 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
25549 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25703 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25857 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26077 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26297 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5a9xx.h24979 #define GTZC_CFGR1_TIM4_Pos (2U) macro
24980 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
25201 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25357 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25513 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25735 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
25957 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
Dstm32u5g9xx.h25939 #define GTZC_CFGR1_TIM4_Pos (2U) macro
25940 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos)
26169 #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26329 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26489 #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26719 #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos
26949 #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos