Home
last modified time | relevance | path

Searched refs:GTZC_CFGR1_TIM4_Msk (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16412 #define GTZC_CFGR1_TIM4_Msk ( 0x01UL << GTZC_CFGR1_TIM4_Pos ) macro
16552 #define GTZC_TZSC_SECCFGR1_TIM4SEC_Msk GTZC_CFGR1_TIM4_Msk
16654 #define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Msk GTZC_CFGR1_TIM4_Msk
16756 #define GTZC_TZIC_IER1_TIM4IE_Msk GTZC_CFGR1_TIM4_Msk
16896 #define GTZC_TZIC_SR1_TIM4F_Msk GTZC_CFGR1_TIM4_Msk
17036 #define GTZC_TZIC_FCR1_TIM4FC_Msk GTZC_CFGR1_TIM4_Msk
Dstm32l562xx.h17151 #define GTZC_CFGR1_TIM4_Msk ( 0x01UL << GTZC_CFGR1_TIM4_Pos ) macro
17297 #define GTZC_TZSC_SECCFGR1_TIM4SEC_Msk GTZC_CFGR1_TIM4_Msk
17403 #define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Msk GTZC_CFGR1_TIM4_Msk
17509 #define GTZC_TZIC_IER1_TIM4IE_Msk GTZC_CFGR1_TIM4_Msk
17655 #define GTZC_TZIC_SR1_TIM4F_Msk GTZC_CFGR1_TIM4_Msk
17801 #define GTZC_TZIC_FCR1_TIM4FC_Msk GTZC_CFGR1_TIM4_Msk
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15742 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
15893 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16000 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16106 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16256 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16406 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32h562xx.h17058 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
17247 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
17392 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
17536 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
17724 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
17912 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32h533xx.h16291 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
16450 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16563 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16675 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16833 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
16991 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32h573xx.h19703 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
19906 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20063 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20219 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20421 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20623 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32h563xx.h19154 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
19349 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19500 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19650 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19844 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20038 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18382 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
18554 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18674 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18794 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18964 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19134 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u535xx.h17830 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
17994 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18108 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18222 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18384 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
18546 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u575xx.h19423 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
19609 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19739 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
19869 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20055 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20241 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u585xx.h20033 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
20229 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20365 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20501 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20697 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20893 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u595xx.h20596 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
20798 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
20938 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21078 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21280 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21482 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5a5xx.h21206 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
21418 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21564 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21710 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
21922 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
22134 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5f7xx.h22189 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
22407 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
22559 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
22711 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
22929 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
23147 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u599xx.h24370 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
24582 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
24732 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
24882 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25094 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25306 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5g7xx.h22799 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
23027 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
23185 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
23343 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
23571 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
23799 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5f9xx.h25330 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
25550 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25704 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25858 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26078 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26298 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5a9xx.h24980 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
25202 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25358 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25514 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25736 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
25958 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
Dstm32u5g9xx.h25940 #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) macro
26170 #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26330 #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26490 #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26720 #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk
26950 #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk