Home
last modified time | relevance | path

Searched refs:GTZC_CFGR1_SPI3_Pos (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h179 #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h205 #define GTZC_PERIPH_SPI3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h340 #define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15757 #define GTZC_CFGR1_SPI3_Pos (12U) macro
15758 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
15908 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16015 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16121 #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16271 #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16421 #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32h562xx.h17077 #define GTZC_CFGR1_SPI3_Pos (12U) macro
17078 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
17266 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
17411 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
17555 #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
17743 #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
17931 #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32h533xx.h16306 #define GTZC_CFGR1_SPI3_Pos (12U) macro
16307 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
16465 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16578 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16690 #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
16848 #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
17006 #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32h573xx.h19722 #define GTZC_CFGR1_SPI3_Pos (12U) macro
19723 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
19925 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20082 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20238 #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20440 #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20642 #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32h563xx.h19173 #define GTZC_CFGR1_SPI3_Pos (12U) macro
19174 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
19368 #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19519 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19669 #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19863 #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20057 #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32h503xx.h10845 #define GTZC_CFGR1_SPI3_Pos (12U) macro
10846 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
10954 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18499 #define GTZC_CFGR1_SPI3_Pos (0U) macro
18500 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
18643 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18763 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18909 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19079 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19247 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u535xx.h17939 #define GTZC_CFGR1_SPI3_Pos (0U) macro
17940 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
18077 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18191 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18329 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18491 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
18651 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u575xx.h19554 #define GTZC_CFGR1_SPI3_Pos (0U) macro
19555 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
19708 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
19838 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20000 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20186 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20372 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u585xx.h20174 #define GTZC_CFGR1_SPI3_Pos (0U) macro
20175 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
20334 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20470 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20642 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
20838 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21034 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u595xx.h20743 #define GTZC_CFGR1_SPI3_Pos (0U) macro
20744 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
20907 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21047 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21225 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21427 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21629 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5a5xx.h21363 #define GTZC_CFGR1_SPI3_Pos (0U) macro
21364 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
21533 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21679 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
21867 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
22079 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
22291 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5f7xx.h22352 #define GTZC_CFGR1_SPI3_Pos (0U) macro
22353 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
22528 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
22680 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
22874 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23092 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23310 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u599xx.h24527 #define GTZC_CFGR1_SPI3_Pos (0U) macro
24528 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
24701 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
24851 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25039 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25251 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25463 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5g7xx.h22972 #define GTZC_CFGR1_SPI3_Pos (0U) macro
22973 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
23154 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23312 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23516 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23744 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
23972 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5f9xx.h25495 #define GTZC_CFGR1_SPI3_Pos (0U) macro
25496 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
25673 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25827 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26023 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26243 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26463 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5a9xx.h25147 #define GTZC_CFGR1_SPI3_Pos (0U) macro
25148 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
25327 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25483 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25681 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
25903 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26125 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
Dstm32u5g9xx.h26115 #define GTZC_CFGR1_SPI3_Pos (0U) macro
26116 #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos)
26299 #define GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26459 #define GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26665 #define GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
26895 #define GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
27125 #define GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16397 #define GTZC_CFGR1_SPI3_Pos (9U) macro
16398 #define GTZC_CFGR1_SPI3_Msk ( 0x01UL << GTZC_CFGR1_SPI3_Pos )
16537 #define GTZC_TZSC_SECCFGR1_SPI3SEC_Pos GTZC_CFGR1_SPI3_Pos
16741 #define GTZC_TZIC_IER1_SPI3IE_Pos GTZC_CFGR1_SPI3_Pos
16881 #define GTZC_TZIC_SR1_SPI3F_Pos GTZC_CFGR1_SPI3_Pos
17021 #define GTZC_TZIC_FCR1_SPI3FC_Pos GTZC_CFGR1_SPI3_Pos
Dstm32l562xx.h17136 #define GTZC_CFGR1_SPI3_Pos (9U) macro
17137 #define GTZC_CFGR1_SPI3_Msk ( 0x01UL << GTZC_CFGR1_SPI3_Pos )
17282 #define GTZC_TZSC_SECCFGR1_SPI3SEC_Pos GTZC_CFGR1_SPI3_Pos
17494 #define GTZC_TZIC_IER1_SPI3IE_Pos GTZC_CFGR1_SPI3_Pos
17640 #define GTZC_TZIC_SR1_SPI3F_Pos GTZC_CFGR1_SPI3_Pos
17786 #define GTZC_TZIC_FCR1_SPI3FC_Pos GTZC_CFGR1_SPI3_Pos