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Searched refs:GTZC_CFGR1_SPI2_Pos (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h178 #define GTZC_PERIPH_SPI2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_gtzc.h204 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h198 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos)
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16399 #define GTZC_CFGR1_SPI2_Pos (8U) macro
16400 #define GTZC_CFGR1_SPI2_Msk ( 0x01UL << GTZC_CFGR1_SPI2_Pos )
16539 #define GTZC_TZSC_SECCFGR1_SPI2SEC_Pos GTZC_CFGR1_SPI2_Pos
16641 #define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Pos GTZC_CFGR1_SPI2_Pos
16743 #define GTZC_TZIC_IER1_SPI2IE_Pos GTZC_CFGR1_SPI2_Pos
16883 #define GTZC_TZIC_SR1_SPI2F_Pos GTZC_CFGR1_SPI2_Pos
17023 #define GTZC_TZIC_FCR1_SPI2FC_Pos GTZC_CFGR1_SPI2_Pos
Dstm32l562xx.h17138 #define GTZC_CFGR1_SPI2_Pos (8U) macro
17139 #define GTZC_CFGR1_SPI2_Msk ( 0x01UL << GTZC_CFGR1_SPI2_Pos )
17284 #define GTZC_TZSC_SECCFGR1_SPI2SEC_Pos GTZC_CFGR1_SPI2_Pos
17390 #define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Pos GTZC_CFGR1_SPI2_Pos
17496 #define GTZC_TZIC_IER1_SPI2IE_Pos GTZC_CFGR1_SPI2_Pos
17642 #define GTZC_TZIC_SR1_SPI2F_Pos GTZC_CFGR1_SPI2_Pos
17788 #define GTZC_TZIC_FCR1_SPI2FC_Pos GTZC_CFGR1_SPI2_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15755 #define GTZC_CFGR1_SPI2_Pos (11U) macro
15756 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
15906 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16013 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16119 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16269 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16419 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32h562xx.h17075 #define GTZC_CFGR1_SPI2_Pos (11U) macro
17076 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
17264 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
17409 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
17553 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
17741 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
17929 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32h533xx.h16304 #define GTZC_CFGR1_SPI2_Pos (11U) macro
16305 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
16463 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16576 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16688 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
16846 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
17004 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32h573xx.h19720 #define GTZC_CFGR1_SPI2_Pos (11U) macro
19721 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
19923 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20080 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20236 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20438 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20640 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32h563xx.h19171 #define GTZC_CFGR1_SPI2_Pos (11U) macro
19172 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
19366 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19517 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19667 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19861 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20055 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32h503xx.h10843 #define GTZC_CFGR1_SPI2_Pos (11U) macro
10844 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
10952 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18393 #define GTZC_CFGR1_SPI2_Pos (8U) macro
18394 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
18565 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18685 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18805 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18975 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19145 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u535xx.h17841 #define GTZC_CFGR1_SPI2_Pos (8U) macro
17842 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
18005 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18119 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18233 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18395 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
18557 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u575xx.h19434 #define GTZC_CFGR1_SPI2_Pos (8U) macro
19435 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
19620 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19750 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
19880 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20066 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20252 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u585xx.h20044 #define GTZC_CFGR1_SPI2_Pos (8U) macro
20045 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
20240 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20376 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20512 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20708 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20904 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u595xx.h20607 #define GTZC_CFGR1_SPI2_Pos (8U) macro
20608 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
20809 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
20949 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21089 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21291 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21493 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5a5xx.h21217 #define GTZC_CFGR1_SPI2_Pos (8U) macro
21218 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
21429 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21575 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21721 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
21933 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
22145 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5f7xx.h22200 #define GTZC_CFGR1_SPI2_Pos (8U) macro
22201 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
22418 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
22570 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
22722 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
22940 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
23158 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u599xx.h24381 #define GTZC_CFGR1_SPI2_Pos (8U) macro
24382 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
24593 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
24743 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
24893 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25105 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25317 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5g7xx.h22810 #define GTZC_CFGR1_SPI2_Pos (8U) macro
22811 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
23038 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
23196 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
23354 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
23582 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
23810 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5f9xx.h25341 #define GTZC_CFGR1_SPI2_Pos (8U) macro
25342 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
25561 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25715 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25869 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26089 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26309 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5a9xx.h24991 #define GTZC_CFGR1_SPI2_Pos (8U) macro
24992 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
25213 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25369 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25525 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25747 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
25969 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
Dstm32u5g9xx.h25951 #define GTZC_CFGR1_SPI2_Pos (8U) macro
25952 #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos)
26181 #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26341 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26501 #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26731 #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos
26961 #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos