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Searched refs:GTZC_CFGR1_LPTIM3_Pos (Results 1 – 16 of 16) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_gtzc.h194 #define GTZC_PERIPH_LPTIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos)
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gtzc.h344 #define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos)
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16367 #define GTZC_CFGR1_LPTIM3_Pos (24U) macro
16368 #define GTZC_CFGR1_LPTIM3_Msk ( 0x01UL << GTZC_CFGR1_LPTIM3_Pos )
16507 #define GTZC_TZSC_SECCFGR1_LPTIM3SEC_Pos GTZC_CFGR1_LPTIM3_Pos
16609 #define GTZC_TZSC_PRIVCFGR1_LPTIM3PRIV_Pos GTZC_CFGR1_LPTIM3_Pos
16711 #define GTZC_TZIC_IER1_LPTIM3IE_Pos GTZC_CFGR1_LPTIM3_Pos
16851 #define GTZC_TZIC_SR1_LPTIM3F_Pos GTZC_CFGR1_LPTIM3_Pos
16991 #define GTZC_TZIC_FCR1_LPTIM3FC_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32l562xx.h17106 #define GTZC_CFGR1_LPTIM3_Pos (24U) macro
17107 #define GTZC_CFGR1_LPTIM3_Msk ( 0x01UL << GTZC_CFGR1_LPTIM3_Pos )
17252 #define GTZC_TZSC_SECCFGR1_LPTIM3SEC_Pos GTZC_CFGR1_LPTIM3_Pos
17358 #define GTZC_TZSC_PRIVCFGR1_LPTIM3PRIV_Pos GTZC_CFGR1_LPTIM3_Pos
17464 #define GTZC_TZIC_IER1_LPTIM3IE_Pos GTZC_CFGR1_LPTIM3_Pos
17610 #define GTZC_TZIC_SR1_LPTIM3F_Pos GTZC_CFGR1_LPTIM3_Pos
17756 #define GTZC_TZIC_FCR1_LPTIM3FC_Pos GTZC_CFGR1_LPTIM3_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18507 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
18508 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
18651 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18771 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18917 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
19087 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
19255 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u535xx.h17947 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
17948 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
18085 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18199 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18337 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18499 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
18659 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u575xx.h19562 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
19563 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
19716 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
19846 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20008 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20194 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20380 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u585xx.h20182 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
20183 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
20342 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20478 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20650 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
20846 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21042 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u595xx.h20751 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
20752 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
20915 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21055 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21233 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21435 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21637 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5a5xx.h21371 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
21372 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
21541 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21687 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
21875 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
22087 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
22299 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5f7xx.h22360 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
22361 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
22536 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
22688 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
22882 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23100 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23318 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u599xx.h24535 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
24536 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
24709 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
24859 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25047 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25259 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25471 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5g7xx.h22980 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
22981 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
23162 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23320 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23524 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23752 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
23980 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5f9xx.h25503 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
25504 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
25681 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25835 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26031 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26251 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26471 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5a9xx.h25155 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
25156 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
25335 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25491 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25689 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
25911 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26133 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
Dstm32u5g9xx.h26123 #define GTZC_CFGR1_LPTIM3_Pos (4U) macro
26124 #define GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos)
26307 #define GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26467 #define GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26673 #define GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
26903 #define GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos
27133 #define GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos