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Searched refs:GTZC_CFGR1_LPTIM2_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h16370 #define GTZC_CFGR1_LPTIM2_Msk ( 0x01UL << GTZC_CFGR1_LPTIM2_Pos ) macro
16510 #define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk GTZC_CFGR1_LPTIM2_Msk
16612 #define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk GTZC_CFGR1_LPTIM2_Msk
16714 #define GTZC_TZIC_IER1_LPTIM2IE_Msk GTZC_CFGR1_LPTIM2_Msk
16854 #define GTZC_TZIC_SR1_LPTIM2F_Msk GTZC_CFGR1_LPTIM2_Msk
16994 #define GTZC_TZIC_FCR1_LPTIM2FC_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32l562xx.h17109 #define GTZC_CFGR1_LPTIM2_Msk ( 0x01UL << GTZC_CFGR1_LPTIM2_Pos ) macro
17255 #define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk GTZC_CFGR1_LPTIM2_Msk
17361 #define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk GTZC_CFGR1_LPTIM2_Msk
17467 #define GTZC_TZIC_IER1_LPTIM2IE_Msk GTZC_CFGR1_LPTIM2_Msk
17613 #define GTZC_TZIC_SR1_LPTIM2F_Msk GTZC_CFGR1_LPTIM2_Msk
17759 #define GTZC_TZIC_FCR1_LPTIM2FC_Msk GTZC_CFGR1_LPTIM2_Msk
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h15784 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
15935 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16042 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16148 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16298 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16448 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32h562xx.h17116 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
17305 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
17450 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
17594 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
17782 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
17970 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32h533xx.h16333 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
16492 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16605 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16717 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
16875 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
17033 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32h573xx.h19761 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
19964 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20121 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20277 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20479 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20681 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32h563xx.h19212 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
19407 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19558 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19708 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19902 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20096 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32h503xx.h10864 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
10969 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h18410 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
18582 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18702 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18822 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18992 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19162 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u535xx.h17858 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
18022 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18136 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18250 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18412 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
18574 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u575xx.h19453 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
19639 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19769 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
19899 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20085 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20271 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u585xx.h20063 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
20259 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20395 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20531 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20727 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20923 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u595xx.h20626 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
20828 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
20968 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21108 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21310 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21512 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5a5xx.h21236 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
21448 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21594 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21740 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
21952 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
22164 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5f7xx.h22219 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
22437 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
22589 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
22741 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
22959 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
23177 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u599xx.h24400 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
24612 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
24762 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
24912 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25124 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25336 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5g7xx.h22829 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
23057 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
23215 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
23373 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
23601 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
23829 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5f9xx.h25360 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
25580 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25734 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25888 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26108 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26328 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5a9xx.h25010 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
25232 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25388 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25544 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25766 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
25988 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
Dstm32u5g9xx.h25970 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
26200 #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26360 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26520 #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26750 #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
26980 #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h5635 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
Dstm32wba54xx.h5818 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
Dstm32wba5mxx.h5818 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro
Dstm32wba55xx.h5818 #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) macro