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Searched refs:GFXTIM_WDGTCR_WDGHRC_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_gfxtim.h516 #define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE (0U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
517 #define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE (1U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
518 #define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE (2U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gfxtim.h516 #define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE (0U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
517 #define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE (1U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
518 #define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE (2U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_gfxtim.h516 #define GFXTIM_WATCHDOG_HW_RELOAD_DISABLE (0U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
517 #define GFXTIM_WATCHDOG_HW_RELOAD_RISING_EDGE (1U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
518 #define GFXTIM_WATCHDOG_HW_RELOAD_FALLING_EDGE (2U << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< Watchdo…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h10142 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
10143 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
10145 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
10146 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32h7s7xx.h10666 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
10667 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
10669 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
10670 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32h7s3xx.h10587 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
10588 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
10590 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
10591 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32h7r7xx.h10219 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
10220 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
10222 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
10223 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9991 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
9992 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
9994 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
9995 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32u5g7xx.h10440 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
10441 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
10443 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
10444 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32u5f9xx.h13117 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
13118 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
13120 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
13121 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32u5g9xx.h13566 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
13567 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
13569 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
13570 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18891 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
18892 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
18894 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
18895 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32n657xx.h19833 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
19834 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
19836 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
19837 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32n655xx.h19591 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
19592 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
19594 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
19595 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
Dstm32n647xx.h19133 #define GFXTIM_WDGTCR_WDGHRC_Pos (4U) macro
19134 #define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
19136 #define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
19137 #define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */