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Searched refs:GFXTIM_WDGTCR_WDGCS_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_gfxtim.h526 #define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */
527 #define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */
528 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising …
529 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling…
530 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising …
531 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling…
532 #define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
533 #define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
534 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
535 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gfxtim.h526 #define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */
527 #define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */
528 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising …
529 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling…
530 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising …
531 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling…
532 #define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
533 #define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
534 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
535 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
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/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_gfxtim.h526 #define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */
527 #define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */
528 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising …
529 #define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling…
530 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising …
531 #define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling…
532 #define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
533 #define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effec…
534 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
535 #define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generat…
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/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h10148 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
10149 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10151 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10152 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10153 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10154 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32h7s7xx.h10672 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
10673 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10675 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10676 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10677 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10678 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32h7s3xx.h10593 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
10594 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10596 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10597 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10598 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10599 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32h7r7xx.h10225 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
10226 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10228 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10229 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10230 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10231 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9997 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
9998 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10000 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10001 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10002 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10003 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32u5g7xx.h10446 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
10447 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
10449 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
10450 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
10451 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
10452 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32u5f9xx.h13123 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
13124 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
13126 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
13127 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
13128 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
13129 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32u5g9xx.h13572 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
13573 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
13575 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
13576 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
13577 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
13578 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18897 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
18898 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
18900 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
18901 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
18902 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
18903 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32n657xx.h19839 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
19840 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
19842 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
19843 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
19844 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
19845 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32n655xx.h19597 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
19598 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
19600 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
19601 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
19602 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
19603 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
Dstm32n647xx.h19139 #define GFXTIM_WDGTCR_WDGCS_Pos (8U) macro
19140 #define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
19142 #define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
19143 #define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
19144 #define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
19145 #define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */