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Searched refs:GFXTIM_EVSR_LES1_Pos (Results 1 – 15 of 15) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_gfxtim.h480 #define GFXTIM_LINE_EVENT_NONE (0U << GFXTIM_EVSR_LES1_Pos) /*!< None */
481 #define GFXTIM_LINE_EVENT_ALC_OVERFLOW (1U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
482 #define GFXTIM_LINE_EVENT_TE (2U << GFXTIM_EVSR_LES1_Pos) /*!< Tearing effect */
483 #define GFXTIM_LINE_EVENT_ALC1_COMPARE (4U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
484 #define GFXTIM_LINE_EVENT_ALC2_COMPARE (5U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_gfxtim.h480 #define GFXTIM_LINE_EVENT_NONE (0U << GFXTIM_EVSR_LES1_Pos) /*!< None */
481 #define GFXTIM_LINE_EVENT_ALC_OVERFLOW (1U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
482 #define GFXTIM_LINE_EVENT_TE (2U << GFXTIM_EVSR_LES1_Pos) /*!< Tearing effect */
483 #define GFXTIM_LINE_EVENT_ALC1_COMPARE (4U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
484 #define GFXTIM_LINE_EVENT_ALC2_COMPARE (5U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_gfxtim.h480 #define GFXTIM_LINE_EVENT_NONE (0U << GFXTIM_EVSR_LES1_Pos) /*!< None */
481 #define GFXTIM_LINE_EVENT_ALC_OVERFLOW (1U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
482 #define GFXTIM_LINE_EVENT_TE (2U << GFXTIM_EVSR_LES1_Pos) /*!< Tearing effect */
483 #define GFXTIM_LINE_EVENT_ALC1_COMPARE (4U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
484 #define GFXTIM_LINE_EVENT_ALC2_COMPARE (5U << GFXTIM_EVSR_LES1_Pos) /*!< Absolute line counter …
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h10073 #define GFXTIM_EVSR_LES1_Pos (0U) macro
10074 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
10076 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
10077 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
10078 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32h7s7xx.h10597 #define GFXTIM_EVSR_LES1_Pos (0U) macro
10598 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
10600 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
10601 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
10602 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32h7s3xx.h10518 #define GFXTIM_EVSR_LES1_Pos (0U) macro
10519 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
10521 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
10522 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
10523 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32h7r7xx.h10150 #define GFXTIM_EVSR_LES1_Pos (0U) macro
10151 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
10153 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
10154 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
10155 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9922 #define GFXTIM_EVSR_LES1_Pos (0U) macro
9923 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
9925 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
9926 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
9927 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32u5g7xx.h10371 #define GFXTIM_EVSR_LES1_Pos (0U) macro
10372 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
10374 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
10375 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
10376 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32u5f9xx.h13048 #define GFXTIM_EVSR_LES1_Pos (0U) macro
13049 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
13051 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
13052 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
13053 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32u5g9xx.h13497 #define GFXTIM_EVSR_LES1_Pos (0U) macro
13498 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
13500 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
13501 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
13502 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18822 #define GFXTIM_EVSR_LES1_Pos (0U) macro
18823 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
18825 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
18826 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
18827 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32n657xx.h19764 #define GFXTIM_EVSR_LES1_Pos (0U) macro
19765 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
19767 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
19768 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
19769 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32n655xx.h19522 #define GFXTIM_EVSR_LES1_Pos (0U) macro
19523 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
19525 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
19526 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
19527 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
Dstm32n647xx.h19064 #define GFXTIM_EVSR_LES1_Pos (0U) macro
19065 #define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
19067 #define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
19068 #define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
19069 #define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */