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Searched refs:GFXTIM_CGCR_LCCHRS_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9965 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
9966 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
9968 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
9969 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
9970 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32h7s7xx.h10489 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
10490 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
10492 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
10493 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
10494 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32h7s3xx.h10410 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
10411 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
10413 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
10414 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
10415 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32h7r7xx.h10042 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
10043 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
10045 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
10046 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
10047 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9814 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
9815 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
9817 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
9818 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
9819 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32u5g7xx.h10263 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
10264 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
10266 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
10267 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
10268 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32u5f9xx.h12940 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
12941 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
12943 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
12944 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
12945 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32u5g9xx.h13389 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
13390 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
13392 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
13393 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
13394 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18714 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
18715 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
18717 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
18718 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
18719 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32n657xx.h19656 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
19657 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
19659 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
19660 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
19661 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32n655xx.h19414 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
19415 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
19417 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
19418 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
19419 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
Dstm32n647xx.h18956 #define GFXTIM_CGCR_LCCHRS_Pos (12U) macro
18957 #define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
18959 #define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
18960 #define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
18961 #define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */