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Searched refs:GFXTIM_CGCR_FCS_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9972 #define GFXTIM_CGCR_FCS_Pos (16U) macro
9973 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
9975 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
9976 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
9977 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32h7s7xx.h10496 #define GFXTIM_CGCR_FCS_Pos (16U) macro
10497 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
10499 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
10500 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
10501 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32h7s3xx.h10417 #define GFXTIM_CGCR_FCS_Pos (16U) macro
10418 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
10420 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
10421 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
10422 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32h7r7xx.h10049 #define GFXTIM_CGCR_FCS_Pos (16U) macro
10050 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
10052 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
10053 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
10054 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9821 #define GFXTIM_CGCR_FCS_Pos (16U) macro
9822 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
9824 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
9825 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
9826 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32u5g7xx.h10270 #define GFXTIM_CGCR_FCS_Pos (16U) macro
10271 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
10273 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
10274 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
10275 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32u5f9xx.h12947 #define GFXTIM_CGCR_FCS_Pos (16U) macro
12948 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
12950 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
12951 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
12952 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32u5g9xx.h13396 #define GFXTIM_CGCR_FCS_Pos (16U) macro
13397 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
13399 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
13400 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
13401 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18721 #define GFXTIM_CGCR_FCS_Pos (16U) macro
18722 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
18724 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
18725 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
18726 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32n657xx.h19663 #define GFXTIM_CGCR_FCS_Pos (16U) macro
19664 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
19666 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
19667 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
19668 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32n655xx.h19421 #define GFXTIM_CGCR_FCS_Pos (16U) macro
19422 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
19424 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
19425 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
19426 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
Dstm32n647xx.h18963 #define GFXTIM_CGCR_FCS_Pos (16U) macro
18964 #define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
18966 #define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
18967 #define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
18968 #define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */