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Searched refs:GFXTIM_CGCR_FCCHRS_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9990 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
9991 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
9993 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
9994 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
9995 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32h7s7xx.h10514 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
10515 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
10517 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
10518 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
10519 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32h7s3xx.h10435 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
10436 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
10438 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
10439 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
10440 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32h7r7xx.h10067 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
10068 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
10070 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
10071 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
10072 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9839 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
9840 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
9842 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
9843 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
9844 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32u5g7xx.h10288 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
10289 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
10291 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
10292 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
10293 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32u5f9xx.h12965 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
12966 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
12968 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
12969 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
12970 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32u5g9xx.h13414 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
13415 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
13417 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
13418 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
13419 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18739 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
18740 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
18742 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
18743 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
18744 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32n657xx.h19681 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
19682 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
19684 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
19685 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
19686 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32n655xx.h19439 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
19440 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
19442 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
19443 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
19444 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
Dstm32n647xx.h18981 #define GFXTIM_CGCR_FCCHRS_Pos (28U) macro
18982 #define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
18984 #define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
18985 #define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
18986 #define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */