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Searched refs:GFXTIM_CGCR_FCCCS_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9979 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
9980 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
9982 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
9983 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
9984 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32h7s7xx.h10503 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
10504 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
10506 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
10507 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
10508 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32h7s3xx.h10424 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
10425 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
10427 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
10428 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
10429 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32h7r7xx.h10056 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
10057 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
10059 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
10060 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
10061 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9828 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
9829 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
9831 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
9832 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
9833 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32u5g7xx.h10277 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
10278 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
10280 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
10281 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
10282 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32u5f9xx.h12954 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
12955 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
12957 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
12958 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
12959 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32u5g9xx.h13403 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
13404 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
13406 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
13407 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
13408 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18728 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
18729 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
18731 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
18732 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
18733 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32n657xx.h19670 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
19671 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
19673 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
19674 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
19675 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32n655xx.h19428 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
19429 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
19431 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
19432 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
19433 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
Dstm32n647xx.h18970 #define GFXTIM_CGCR_FCCCS_Pos (20U) macro
18971 #define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
18973 #define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
18974 #define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
18975 #define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */