/hal_stm32-latest/stm32cube/stm32l4xx/soc/ |
D | stm32l4r7xx.h | 9324 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9325 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32l4s7xx.h | 9576 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9577 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32l4r9xx.h | 12443 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 12444 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32l4s9xx.h | 12695 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 12696 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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/hal_stm32-latest/stm32cube/stm32h7xx/soc/ |
D | stm32h7a3xx.h | 9601 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9602 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7b0xx.h | 9848 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9849 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7b0xxq.h | 9849 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9850 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7a3xxq.h | 9602 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9603 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7b3xx.h | 9855 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9856 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7b3xxq.h | 9856 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9857 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/ |
D | stm32h7r3xx.h | 9898 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9899 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7s7xx.h | 10422 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 10423 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7s3xx.h | 10343 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 10344 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32h7r7xx.h | 9975 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9976 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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/hal_stm32-latest/stm32cube/stm32u5xx/soc/ |
D | stm32u5f7xx.h | 9748 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 9749 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32u599xx.h | 12756 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 12757 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32u5g7xx.h | 10197 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 10198 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32u5f9xx.h | 12874 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 12875 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32u5a9xx.h | 13205 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 13206 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32u5g9xx.h | 13323 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 13324 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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/hal_stm32-latest/stm32cube/stm32n6xx/soc/ |
D | stm32n645xx.h | 18647 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 18648 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32n657xx.h | 19589 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 19590 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32n655xx.h | 19347 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 19348 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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D | stm32n647xx.h | 18889 #define GFXMMU_B3CR_PBBA_Pos (23U) macro 18890 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
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