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Searched refs:GFXMMU_B1CR_PBO_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r7xx.h9305 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9306 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32l4s7xx.h9557 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9558 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32l4r9xx.h12424 #define GFXMMU_B1CR_PBO_Pos (4U) macro
12425 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32l4s9xx.h12676 #define GFXMMU_B1CR_PBO_Pos (4U) macro
12677 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h9582 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9583 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7b0xx.h9829 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9830 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7b0xxq.h9830 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9831 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7a3xxq.h9583 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9584 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7b3xx.h9836 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9837 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7b3xxq.h9837 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9838 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h9879 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9880 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7s7xx.h10403 #define GFXMMU_B1CR_PBO_Pos (4U) macro
10404 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7s3xx.h10324 #define GFXMMU_B1CR_PBO_Pos (4U) macro
10325 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32h7r7xx.h9956 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9957 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u5f7xx.h9729 #define GFXMMU_B1CR_PBO_Pos (4U) macro
9730 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32u599xx.h12737 #define GFXMMU_B1CR_PBO_Pos (4U) macro
12738 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32u5g7xx.h10178 #define GFXMMU_B1CR_PBO_Pos (4U) macro
10179 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32u5f9xx.h12855 #define GFXMMU_B1CR_PBO_Pos (4U) macro
12856 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32u5a9xx.h13186 #define GFXMMU_B1CR_PBO_Pos (4U) macro
13187 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32u5g9xx.h13304 #define GFXMMU_B1CR_PBO_Pos (4U) macro
13305 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h18628 #define GFXMMU_B1CR_PBO_Pos (4U) macro
18629 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32n657xx.h19570 #define GFXMMU_B1CR_PBO_Pos (4U) macro
19571 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32n655xx.h19328 #define GFXMMU_B1CR_PBO_Pos (4U) macro
19329 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
Dstm32n647xx.h18870 #define GFXMMU_B1CR_PBO_Pos (4U) macro
18871 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */