Searched refs:FSMC_BTRx_ADDSET_Pos (Results 1 – 9 of 9) sorted by relevance
5171 #define FSMC_BTRx_ADDSET_Pos (0U) macro5172 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */5174 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */5175 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */5176 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */5177 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
5038 #define FSMC_BTRx_ADDSET_Pos (0U) macro5039 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */5041 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */5042 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */5043 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */5044 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
4963 #define FSMC_BTRx_ADDSET_Pos (0U) macro4964 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */4966 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */4967 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */4968 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */4969 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
5191 #define FSMC_BTRx_ADDSET_Pos (0U) macro5192 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */5194 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */5195 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */5196 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */5197 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
5261 #define FSMC_BTRx_ADDSET_Pos (0U) macro5262 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */5264 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */5265 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */5266 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */5267 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
345 (Timing->AddressSetupTime << FSMC_BTRx_ADDSET_Pos) | in FSMC_NORSRAM_Timing_Init()
3362 #define FSMC_BTRx_ADDSET_Pos (0U) macro3363 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */3365 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */3366 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */3367 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */3368 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
3379 #define FSMC_BTRx_ADDSET_Pos (0U) macro3380 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */3382 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */3383 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */3384 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */3385 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
3509 #define FSMC_BTRx_ADDSET_Pos (0U) macro3510 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */3512 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */3513 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */3514 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */3515 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
