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Searched refs:FCR (Results 1 – 25 of 274) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_lcd.h530 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
536 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
558 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
579 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
600 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
628 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
642 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
647 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
662 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_lcd.h383 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
393 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
427 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
448 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
469 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
497 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
511 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
525 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
540 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_lcd.h514 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
520 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
542 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
563 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
584 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
612 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
626 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
631 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
646 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_hal_lcd.h383 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
393 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
427 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
448 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
469 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
497 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
511 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
525 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
540 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_lcd.h381 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
391 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
425 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
446 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
467 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
495 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
509 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
523 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
538 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_icache.c170 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
212 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
287 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
331 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
455 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
468 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_icache.c170 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
212 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
287 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
331 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
455 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
468 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_icache.c199 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
246 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
321 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
365 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
489 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
502 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_icache.c199 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
246 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
321 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
365 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
489 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
502 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_icache.c199 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
246 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
321 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
365 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
489 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
502 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_icache.c201 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); in HAL_ICACHE_DeInit()
250 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Disable()
325 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_Invalidate_IT()
369 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_WaitForInvalidateComplete()
493 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); in HAL_ICACHE_IRQHandler()
506 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); in HAL_ICACHE_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h1248 …DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); in LL_DMA_GetFIFOStatus()
1268 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableFifoMode()
1288 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableFifoMode()
1313 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_SetFIFOThreshold()
1337 …MA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); in LL_DMA_GetFIFOThreshold()
1366 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_ConfigFifo()
2618 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableIT_FE()
2718 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableIT_FE()
2818 …Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) ==… in LL_DMA_IsEnabledIT_FE()
Dstm32f2xx_hal_dma.h400 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
567 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
582 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)…
598 … ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h1281 …DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); in LL_DMA_GetFIFOStatus()
1301 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableFifoMode()
1321 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableFifoMode()
1346 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_SetFIFOThreshold()
1370 …MA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); in LL_DMA_GetFIFOThreshold()
1399 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_ConfigFifo()
2651 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableIT_FE()
2751 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableIT_FE()
2851 …Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) ==… in LL_DMA_IsEnabledIT_FE()
Dstm32f7xx_hal_dma.h384 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
551 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
566 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)…
582 … ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h1258 …DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); in LL_DMA_GetFIFOStatus()
1278 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableFifoMode()
1298 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableFifoMode()
1323 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_SetFIFOThreshold()
1347 …MA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); in LL_DMA_GetFIFOThreshold()
1376 …MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_ConfigFifo()
2628 …SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA… in LL_DMA_EnableIT_FE()
2728 …CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, D… in LL_DMA_DisableIT_FE()
2828 …Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) ==… in LL_DMA_IsEnabledIT_FE()
Dstm32f4xx_hal_dma.h410 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
577 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
592 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)…
608 … ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_dma.c255 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
287 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
350 hdma->Instance->FCR = (uint32_t)0x00000021U; in HAL_DMA_DeInit()
482 hdma->Instance->FCR |= DMA_IT_FE; in HAL_DMA_Start_IT()
536 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
860 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_dma.h1507 …return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA… in LL_DMA_GetFIFOStatus()
1529 …CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_… in LL_DMA_DisableFifoMode()
1551 …SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DM… in LL_DMA_EnableFifoMode()
1578 …MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR… in LL_DMA_SetFIFOThreshold()
1604 …return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA… in LL_DMA_GetFIFOThreshold()
1635 …MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR… in LL_DMA_ConfigFifo()
2919 …SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FE… in LL_DMA_EnableIT_FE()
3029 …CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_… in LL_DMA_DisableIT_FE()
3139 …return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DM… in LL_DMA_IsEnabledIT_FE()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h1650 …return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA… in LL_DMA_GetFIFOStatus()
1672 …CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_… in LL_DMA_DisableFifoMode()
1694 …SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DM… in LL_DMA_EnableFifoMode()
1721 …MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR… in LL_DMA_SetFIFOThreshold()
1747 …return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA… in LL_DMA_GetFIFOThreshold()
1778 …MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR… in LL_DMA_ConfigFifo()
3062 …SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FE… in LL_DMA_EnableIT_FE()
3172 …CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_… in LL_DMA_DisableIT_FE()
3282 …return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DM… in LL_DMA_IsEnabledIT_FE()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_hal_dma.c256 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
288 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
351 hdma->Instance->FCR = 0x00000021U; in HAL_DMA_DeInit()
536 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
859 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dma.c253 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
285 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
348 hdma->Instance->FCR = 0x00000021U; in HAL_DMA_DeInit()
533 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
855 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_dcache.h565 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF); in LL_DCACHE_ClearFlag_BSYEND()
576 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF); in LL_DCACHE_ClearFlag_ERR()
587 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF); in LL_DCACHE_ClearFlag_CMDEND()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_dcache.h565 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF); in LL_DCACHE_ClearFlag_BSYEND()
576 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF); in LL_DCACHE_ClearFlag_ERR()
587 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF); in LL_DCACHE_ClearFlag_CMDEND()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_dma.c263 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; in HAL_DMA_Init()
295 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; in HAL_DMA_Init()
398 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; in HAL_DMA_DeInit()
654 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
1027 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()

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