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Searched refs:EWCR (Results 1 – 25 of 70) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
428 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
428 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
417 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
428 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
428 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); in LL_IWDG_ClearFlag_EWIF()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_iwdg.h285 MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); in LL_IWDG_SetEwiTime()
296 return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); in LL_IWDG_GetEwiTime()
307 SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_EnableIT_EWI()
318 CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); in LL_IWDG_DisableIT_EWI()
329 return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); in LL_IWDG_IsEnabledIT_EWI()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_iwdg.c233 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
240 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
428 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_iwdg.c248 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
465 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_iwdg.c248 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
465 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_iwdg.c248 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
465 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_iwdg.c248 hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; in HAL_IWDG_Init()
465 hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; in HAL_IWDG_IRQHandler()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_iwdg.c251 hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | hiwdg->Init.EWI; in HAL_IWDG_Init()
255 hiwdg->Instance->EWCR = 0x00U; in HAL_IWDG_Init()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h458 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32wba52xx.h549 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32wba54xx.h566 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32wba5mxx.h566 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32wba55xx.h566 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
/hal_stm32-latest/stm32cube/stm32u0xx/soc/
Dstm32u031xx.h387 __IO uint32_t EWCR; /*!< IWDG wake-up interrupt register, Address offset: 0x14 */ member
Dstm32u083xx.h433 __IO uint32_t EWCR; /*!< IWDG wake-up interrupt register, Address offset: 0x14 */ member
Dstm32u073xx.h399 __IO uint32_t EWCR; /*!< IWDG wake-up interrupt register, Address offset: 0x14 */ member
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h1081 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32h523xx.h1384 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
Dstm32h562xx.h1474 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h1416 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h1089 __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ member

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