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Searched refs:DSI_GPDR_DATA3_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f469xx.h7606 #define DSI_GPDR_DATA3_Pos (16U) macro
7607 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
7609 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
7610 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
7611 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
7612 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
7613 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
7614 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
7615 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
7616 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32f479xx.h7796 #define DSI_GPDR_DATA3_Pos (16U) macro
7797 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
7799 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
7800 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
7801 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
7802 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
7803 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
7804 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
7805 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
7806 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f779xx.h19595 #define DSI_GPDR_DATA3_Pos (16U) macro
19596 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
19598 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
19599 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
19600 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
19601 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
19602 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
19603 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
19604 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
19605 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32f769xx.h19302 #define DSI_GPDR_DATA3_Pos (16U) macro
19303 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
19305 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
19306 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
19307 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
19308 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
19309 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
19310 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
19311 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
19312 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r9xx.h8970 #define DSI_GPDR_DATA3_Pos (16U) macro
8971 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
8973 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
8974 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
8975 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
8976 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
8977 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
8978 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
8979 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
8980 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32l4s9xx.h9222 #define DSI_GPDR_DATA3_Pos (16U) macro
9223 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
9225 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
9226 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
9227 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
9228 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
9229 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
9230 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
9231 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
9232 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h757xx.h10797 #define DSI_GPDR_DATA3_Pos (16U) macro
10798 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
10800 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
10801 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
10802 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
10803 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
10804 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
10805 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
10806 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
10807 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32h747xg.h10604 #define DSI_GPDR_DATA3_Pos (16U) macro
10605 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
10607 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
10608 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
10609 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
10610 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
10611 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
10612 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
10613 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
10614 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32h747xx.h10604 #define DSI_GPDR_DATA3_Pos (16U) macro
10605 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
10607 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
10608 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
10609 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
10610 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
10611 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
10612 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
10613 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
10614 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u599xx.h8197 #define DSI_GPDR_DATA3_Pos (16U) macro
8198 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
8200 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
8201 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
8202 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
8203 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
8204 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
8205 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
8206 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
8207 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32u5f9xx.h8330 #define DSI_GPDR_DATA3_Pos (16U) macro
8331 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
8333 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
8334 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
8335 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
8336 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
8337 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
8338 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
8339 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
8340 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32u5a9xx.h8646 #define DSI_GPDR_DATA3_Pos (16U) macro
8647 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
8649 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
8650 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
8651 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
8652 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
8653 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
8654 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
8655 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
8656 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
Dstm32u5g9xx.h8779 #define DSI_GPDR_DATA3_Pos (16U) macro
8780 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
8782 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
8783 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
8784 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
8785 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
8786 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
8787 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
8788 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
8789 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */