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Searched refs:DSI_GPDR_DATA2_Pos (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f469xx.h7594 #define DSI_GPDR_DATA2_Pos (8U) macro
7595 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
7597 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
7598 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
7599 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
7600 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
7601 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
7602 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
7603 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
7604 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32f479xx.h7784 #define DSI_GPDR_DATA2_Pos (8U) macro
7785 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
7787 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
7788 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
7789 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
7790 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
7791 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
7792 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
7793 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
7794 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f779xx.h19583 #define DSI_GPDR_DATA2_Pos (8U) macro
19584 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
19586 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
19587 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
19588 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
19589 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
19590 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
19591 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
19592 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
19593 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32f769xx.h19290 #define DSI_GPDR_DATA2_Pos (8U) macro
19291 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
19293 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
19294 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
19295 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
19296 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
19297 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
19298 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
19299 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
19300 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r9xx.h8958 #define DSI_GPDR_DATA2_Pos (8U) macro
8959 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
8961 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
8962 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
8963 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
8964 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
8965 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
8966 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
8967 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
8968 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32l4s9xx.h9210 #define DSI_GPDR_DATA2_Pos (8U) macro
9211 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
9213 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
9214 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
9215 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
9216 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
9217 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
9218 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
9219 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
9220 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h757xx.h10785 #define DSI_GPDR_DATA2_Pos (8U) macro
10786 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
10788 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
10789 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
10790 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
10791 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
10792 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
10793 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
10794 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
10795 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32h747xg.h10592 #define DSI_GPDR_DATA2_Pos (8U) macro
10593 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
10595 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
10596 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
10597 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
10598 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
10599 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
10600 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
10601 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
10602 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32h747xx.h10592 #define DSI_GPDR_DATA2_Pos (8U) macro
10593 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
10595 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
10596 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
10597 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
10598 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
10599 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
10600 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
10601 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
10602 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u599xx.h8185 #define DSI_GPDR_DATA2_Pos (8U) macro
8186 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
8188 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
8189 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
8190 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
8191 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
8192 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
8193 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
8194 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
8195 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32u5f9xx.h8318 #define DSI_GPDR_DATA2_Pos (8U) macro
8319 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
8321 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
8322 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
8323 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
8324 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
8325 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
8326 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
8327 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
8328 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32u5a9xx.h8634 #define DSI_GPDR_DATA2_Pos (8U) macro
8635 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
8637 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
8638 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
8639 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
8640 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
8641 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
8642 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
8643 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
8644 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
Dstm32u5g9xx.h8767 #define DSI_GPDR_DATA2_Pos (8U) macro
8768 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
8770 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
8771 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
8772 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
8773 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
8774 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
8775 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
8776 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
8777 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */