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Searched refs:DMA_CCR_TEIE (Results 1 – 25 of 186) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_dma.h233 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1790 …IT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
1847 …IT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
1907 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32c0xx_hal_dma.h303 #define DMA_IT_TE DMA_CCR_TEIE
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_dma.h236 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1940 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2000 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2063 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_dma.h224 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1801 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
1858 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
1918 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); in LL_DMA_IsEnabledIT_TE()
Dstm32f1xx_hal_dma.h234 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_dma.h255 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1972 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2029 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2089 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32l0xx_hal_dma.h339 #define DMA_IT_TE DMA_CCR_TEIE
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_dma.h241 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2004 SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2061 CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2121 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_dma.h247 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2101 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2161 …EAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2224 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32u0xx_hal_dma.h350 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interru…
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_dma.h250 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2108 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2168 …EAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2231 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32g0xx_hal_dma.h382 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interru…
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_dma.h225 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1837 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
1894 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
1954 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); in LL_DMA_IsEnabledIT_TE()
Dstm32f3xx_hal_dma.h232 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_dma.h226 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
1838 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
1895 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
1955 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); in LL_DMA_IsEnabledIT_TE()
Dstm32l1xx_hal_dma.h234 #define DMA_IT_TE DMA_CCR_TEIE
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_dma.h238 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2327 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2387 …EAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2450 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32wlxx_hal_dma.h304 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interru…
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_dma.h256 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2077 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2134 …nel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2194 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); in LL_DMA_IsEnabledIT_TE()
Dstm32f0xx_hal_dma.h234 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_dma.h273 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2269 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2329 …EAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2392 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32l4xx_hal_dma.h510 #define DMA_IT_TE DMA_CCR_TEIE
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_dma.h240 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2720 …SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2783 …EAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2849 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()
Dstm32l5xx_hal_dma.h385 #define DMA_IT_TE DMA_CCR_TEIE
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_dma.h266 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
2403 …A_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE); in LL_DMA_EnableIT_TE()
2469 …A_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE); in LL_DMA_DisableIT_TE()
2538 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); in LL_DMA_IsEnabledIT_TE()

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